VHDL Reference '93
Design entities and configurations
Entity
Architecture
Configuration
Subprograms and packages
Subprogram declaration
Subprogram body
Overloading
Resolution function
Package declaration
Package body
Conformance rules
Types
Scalar types
Compound types
Access types
File types
Declarations
Type declarations
Subtype declarations
Constant declarations
Signal declarations
Variable declarations
File declarations
Interface declarations
Alias declarations
Attribute declarations
Component declarations
Group template declarations
Group declaration
Specification
Attribute specification
Configuration specification
Disconnection specification
Names
Name
Simple names
Selected names
Indexed names
Range names
Attribute names
Expressions
Expression
Logic operators
Relational operators
Shift Operators
Adding operators
Multiplying operators
Miscellaneous operators
Literals
Aggregates
Function call
Qualified Expression
Type conversion
Allocator
Static expression
Universal expression
Sequential statements
Wait
Assertion
Report
Signal assignment
Variable assignment
Procedure call
IF
CASE
LOOP
NEXT
EXIT
RETURN
NULL
Concurrent statements
Block
Process
Concurrent procedure call
Concurrent assertion
Concurrent signal assignment
Component instantiation
Generate statement
Miscellaneous
Visibility and validity ranges
Use-statements
Design units and their analysis
Elaboration and simulation
Elaboration of a blockheader
Elaboration of a declaration
Elaboration of a statement part
Dynamic elaboration
Elaboration of a design hierarchy
Execution of a model
Lexical elements
Character set
Delimiters
Identifiers
Abstract literals
Character literals
String literals
Bit string literals
Comments
Reserved words
Replacing characters
Predefined attributes
Package STANDARD
Package TEXTIO
BNF