vhdl_reference_93:loop

LOOP

[ loop _label : ]
  [ iteration_scheme ] loop
      sequence_of_statements
  end loop [ loop _label ] ;
  • function_statement_part
  • procedure_statement_part
  • process_statement_part

This is an endless loop in which the signal q is assigned the value of d 1 ns after the condition clock =`1` has been fulfilled.

LOOP
   WAIT UNTIL clock = '1' ;
   q <= d AFTER 1 ns ;
END LOOP ;

This loop, which has a label, is run six times. In each pass the value of var is raised by 5.

lbl : FOR i IN 0 TO 5 LOOP
         var := var + 5 ;
      END LOOP ;

The While-loop is run as long as value > 0 is valid. The statements within the loop are ignored if value = 3 .

WHILE value > 0 LOOP
   NEXT WHEN value = 3 ;
   tab( value ) := value REM 2 ;
   value := value / 2 ;
END LOOP ;

These are two examples for chained FOR -loops which are needed to calculate the values of the elements of a two-dimensional array.

In the second example each of the FOR -loops has its own label. With the EXIT -statement the inner loop is left if i = j .

FOR i IN 10 DOWNTO 2 LOOP
   FOR j IN 0 TO i LOOP
      table( i, j ) := i + j - 7 ;
   END LOOP ;
END LOOP ;
lbl_1 : FOR i IN 10 DOWNTO 2 LOOP
   lbl_2 : FOR j IN 0 TO i LOOP
      EXIT lbl_2 WHEN i = j ;
      table ( i, j ) := i + j - 7 ;
   END LOOP lbl_2 ;
END LOOP lbl_1 ;