Configuration specification

for component_specification binding_indication ;

• architecture_declarative_part
• block_declarative_part

instantiation_list : component _name

[ use entity_aspect ]

[ generic_map_aspect ]

[ port_map_aspect ]

In the generic map aspect an actual must be an expression or the reserved word OPEN .

In the port map aspect an actual must be a signal, an expression or the reserved word OPEN . (In VHDL'87 only signals could be connected with input ports; in VHDL'93 globally static values can be used.)

For the components add_comp of the labels c1 , c2 and c3 the behavioural description add_1 from the default-library ( work ) is to be used.

In all other labels ( OTHERS ) the description add_configuration from the default-library ( work ) is to be used for the components add_comp.

FOR c1, c2, c3 : add_comp USE
   ENTITY work.add_1( behaviour ) ;
 
FOR OTHERS : add_comp USE
   CONFIGURATION work.add_configuration;

All components register_comp which are used are not to be linked.

FOR ALL : register_comp USE OPEN ;

For the components nand2_comp of the labels c(1) to c(5) the entity nand with the generic N=2 and the corresponding in-/output concatenation ( PORT MAP ) is to be used.

For the component nand2_comp of the label c(6) the configuration nand2_configuration from the library my_lib is to be used with the corresponding in-/output concatenation ( PORT MAP ).

FOR c( 1 TO 5 ) : nand2_comp USE
      ENTITY nand( arc )
         GENERIC MAP ( N => 2 )
         PORT MAP ( I(1) => a, I(2) => b, O => s ) ;
 
FOR c(6) : nand2_comp USE
      CONFIGURATION
            my_lib.nand2_configuration
      PORT MAP ( a, b, s ) ;