Architecture

architecture identifier of
     entity _name is
architecture_declarative_part
begin
    architecture_statement_part
end [ architecture ]
        [ architecture _simple_name ] ;

• basic_identifier
• extended_identifier

• simple_name
• operator_symbol
• selected_name
• indexed_name
• slice_name
• attribute_name

{ block_declarative_item }

{ concurrent_statement }

• identifier

Example of an empty architecture of the entity box .

ARCHITECTURE arch OF box IS
BEGIN
END arch ;

Example of an architecture of the entity fulladder . A and B are the necessary internal intermediate signals.

In the architecture-body there are several concurrent instructions which describe the function of the fulladder.

ARCHITECTURE rtl OF fulladder IS
   SIGNAL A,B: Bit ;
BEGIN
   A <= X XOR Y ;
   B <= A AND Cin ;
   Sum <= A XOR Cin ;
   Cout <= B OR (X AND Y) ;
END rtl ;

Example of two different architectures for the entity entity1 . rtl1 : Definition of the required constant delay and the intermediate signal S .

Two concurrent signal assignments with time delays and the function czbit being called.

ARCHITECTURE rtl1 OF entity1 IS
   CONSTANT delay: Time :=5 ns;
   SIGNAL S: Bit;
BEGIN
   S2 <= czbit(S) AFTER 3 ns ;
   S <= S1 AFTER delay ;
END rtl1 ;

rtl2 : Definition and initialization of the intermediate signal S .

Definition of the procedure proc with a signal transfer from A and B .

Conditional signal assignment to B .

Three concurrent instructions named P1 , P2 and P3 .

• P1 is a procedure call.
• P2 assigns a signal by calling a function.
• P3 is a process during which the variable V is declared and then given the value of S by assignment.

ARCHITECTURE rtl2 OF entity1 IS
   SIGNAL S: Bit :='1' ;
 
   PROCEDURE proc( SIGNAL A: IN Bit
      SIGNAL B: INOUT Bit) IS
   BEGIN
      B <= NOT B WHEN A ='1' ELSE B ;
   END proc ;
 
BEGIN
   P1: proc(S1,S);
   P2: S2 <= czbit(S) AFTER 2 ns ;
   P3: PROCESS (S)
      VARIABLE V :Bit ;
   BEGIN
      V := S ;
   END PROCESS P3;
END rtl2 ;