vhdl_reference_93:component_declarations

Component declarations

component identifier [ is ]
    local _generic_clause ]
    [ local _port_clause ]
end component [ component _simple_name ] ;
  • architecture_declarative_part
  • package
  • block_declarative_part

generic ( generic_list ) ;

port ( port_list ) ;

The component gen_clock is declared whose only interface to the outside is the output clk.

COMPONENT gen_clock
   PORT ( clk : OUT tri_bit ) ;
END COMPONENT ;

The component adder_8_bit declared here has the inputs a , b and cin and the outputs sum and cout .

COMPONENT adder_8_bit
   PORT (a, b : IN bit_vector(1 TO 8);
         cin : IN bit ;
         sum : OUT bit_vector(1 TO 8);
         cout: OUT bit ) ;
END COMPONENT ;

The component adder_n_bit declared here is parameterised via the generic n.

The width of the input vectors a and b and that of the output vector sum is determined by the value of the generic n .

COMPONENT adder_n_bit
   GENERIC ( n : positive ) ;
   PORT (a, b : IN bit_vector(1 TO n);
         cin : IN bit ;
         sum : OUT bit_vector(1 TO n);
         cout: OUT bit ) ;
END COMPONENT ;