vhdl_reference_93:wait

Wait

[ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ;
  • function_statement_part
  • procedure_statement_part
  • process_statement_part

until condition

for time _expression

The WAIT-statement must not be used within a function or procedure which itself is called within a function.

The WAIT-statement must not be called by a process which possesses a sensitivity list.

In general the WAIT-statement is ,sensitiveā€œ to all signals used within the statement, except a sensitivity list is used (like in a WAIT ON-statement like in the last example).

In a postponed process the condition in a WAIT statement may already be false at the actual time (last delta cycle) when the process execution is resumed.

The process is permanently interrupted.

WAIT ;

The process is interrupted for 5 ns.

WAIT FOR 5 ns ;

The process is interrupted until the value of one of the two signals changes.

WAIT ON sig_1, sig_2 ;

The process is interrupted until the value of clock is 1.

WAIT UNTIL clock = '1' ;

The process is interrupted until the value of data = good or 25 ns have passed.

WAIT UNTIL data = good FOR 25 ns ;

Initially one waits for the signals sig_1, sig_2 and sig_3 to change; if clock is 1 the process is resumed otherwise not; the process is suspended for at most 25ns.

WAIT ON sig_1, sig_2, sig_3
      UNTIL clock = '1' FOR 25 ns ;