vhdl_reference_93:elaboration_and_simulation

Elaboration and simulation

Elaboration is defined for declarations, draft hierarchies and statements (including concurrent statements). A construct can only be activated by elaboration. As long as elaboration is not finished the corresponding construct does not exist!

Simulation Flow

In order to execute a model it is at first necessary to elaborate the draft hierarchy which describes the model.

Afterwards the model`s nets are initialised and after that model simulation is started. Simulation includes several runs of the simulation cycle. During that processes are executed and netlist parameters are newly calculated or updated.