vhdl_reference_93:range_names

Range names

Different slices are addressed.

  • The first slice addresses the range 0 to 7 of r15 .
  • The second slice addresses the range 24 to 1 of data .
  • The third slice is invalid as the direction of indication in the declaration is opposed to that in the slice.
SIGNAL r15 : bit_vector( 0 TO 31 ) ;
CONSTANT data : bit_vector(31 DOWNTO 0);
 
r15( 0 TO 7 ) ;
data( 24 DOWNTO 1 ) ;
data( 24 TO 25 ) ;