instantiation _label :
    instantiated_unit
        [ generic_map_aspect ]
        [ port_map_aspect ] ;

• architecture_statement_part
• block_statement_part

[ component ] component _name

entity entity _name [ ( architecture _identifier ) ]

configuration configuration _name

generic map ( generic _association_list )

port map ( port _association_list )

In VHDL'87 it was only possible to instantiate components. In VHDL'93 it is allowed to instantiate entities and also configurations.

For an instantiation of a component this component must have been declared before.

For the instantiation of an entity or a configuration these have to be compiled into a library. This library has to be visible when compiling the instantiations.

my_component is integrated into the current architecture without a Port-Map.

c_1 : my_component ;

The component add_n is instantiated with the generic value 8 . In this process the signal s8 is linked to the ports Vss , a8 , b8 , sum and sig is linked to the port cout of the instantiated component.

c : add_n
   GENERIC MAP (8)
   PORT MAP (
      Vss, a8, b8, sum => s8,
      cout          => sig ) ;

The entity my_entity is directly instantiated. The signals I1 and I2 of my_entity are connected with the local signals S1 and S2.

u_myent: ENTITY
   work.my_entity(beh)
   PORT MAP (I1 => S1 , I2 => S2 ) ;

The configuration my_cfg is instantiated. The signals I1 and I2 of the entity linked by the configuration are connected with the local signals S1 and S2.

u_config: CONFIGURATION
   work.my_cfg
   PORT MAP (I1 => S1 , I2 => S2 ) ;

When ram_comp is instantiated the generics nb_data and nb_addr are pre-seized. The signals are linked to the ports of ram_comp by name assignment; the port ready is not linked.

the_ram : ram_comp
   GENERIC MAP (
      nb_data => 8,
      nb_addr => 5 )
   PORT MAP (
      cs   => cs,
      rw   => rw,
      d    => data,
      a    => address,
      ready => OPEN ) ; 

This example is to clarify the interrelationships.

• ← Component-declaration
• ← Component-instantiation with linking of ports
• ← Declaration of the configuration (For comp the architecture y of the entity x is to be used.)
• ← Entity-declaration ( check_timing is a passive procedure!)
• ← Architecture-declaration

COMPONENT comp PORT (a , b : INOUT bit);
 
c : comp PORT MAP ( a => s1, b => s2 ) ;
 
   FOR c : comp USE
      ENTITY x(y) ;
      PORT MAP ( p1 => a, p2 => b ) ;
         ...
 
 
ENTITY x IS
   PORT ( p1, p2 : INOUT bit )
   CONSTANT delay : time := 1 ms ;
BEGIN
   check_timing( p1, p2, 2 * delay ) ;
END x ;
 
ARCHITECTURE y OF x IS
   SIGNAL p3 : bit ;
BEGIN
   p3 <= p1 AFTER delay ;
   p2 <= p3 AFTER delay ;
      b : BLOCK
         ...
      BEGIN
         ...
      END BLOCK ;
END y ;

This is the code which is equivalent to that above:

• ← Component block
• ← local ports
• ← Port concatenation
• ← Entity block
• ← formal ports
• ← Port concatenation
• ← Agreement within the entity
• ← Agreement within the architecture
• ← Architecture statements
• ← internal block hierarchy

c : BLOCK
   PORT ( a, b : INOUT bit ) ;
   PORT MAP ( a => s1, b => s2 ) ;
BEGIN
   x : BLOCK
      PORT ( p1, p2 : INOUT bit ) ;
      PORT MAP ( p1 => a, p2 => b ) ;
      CONSTANT delay : time := 1 ms ;
      SIGNAL p3 : bit ;
   BEGIN
      check_timing(p1, p2, 2 * delay) ;
      p3 <= p1 AFTER delay ;
      p2 <= p3 AFTER delay ;
         b : BLOCK
               ...
         BEGIN
               ...
         END BLOCK ;
   END BLOCK x ;
END BLOCK c ;