vhdl_reference_93:entity

Entity

entity identifier is
    entity_header
    entity_declarative_part
[ begin
    entity_statement_part ]
end [ entity ] [ entity _simple_name ] ;

[ formal _generic_clause ]
[ formal _port_clause ]

Example of a testbench which possesses neither inputs nor outputs.

ENTITY testbench IS
END testbench ;

Entity for a 2-Bit-fulladder.

  • X , Y and Cin are Bit type inputs.
  • Cout and Sum are Bit type outputs.
ENTITY fulladder IS
   PORT (X,Y,Cin   : IN  Bit;
         Cout, Sum : OUT Bit);
END fulladder ;

Entity with several features:

  • Definition of a parameter m .
  • b1 and b2 are inputs (Bits), b3 is an output-vector with the width m .
  • Definition of type byte as a bit-vector.
  • Integrating the objects from the package timing_library . Definition and initialisation of a constant setup time.

Definition of procedure init with signal transfer. Seizing of b4 with several `1` is carried out only after delay .

Instructions within the entity:

  • If the condition which is to be checked is not fulfilled an error is reported. Error is the severity level.
  • A passive procedure (signal assignments in the entity are not allowed!) with b4 and delay as transfer values is called.
ENTITY big_example IS
   GENERIC (m : Positive);
   PORT (b1,b2 : IN Bit;
         b3: OUT Bit_Vector(1 to m));
   TYPE byte IS ARRAY (1 TO 8) OF Bit;
   USE work.timing_library.all;
   CONSTANT setuptime : Time := 12 ns;
 
 
   PROCEDURE init ( SIGNAL b4 : OUT byte) IS
   BEGIN
      b4 <= ( OTHERS => '1') AFTER delay;
   END init;
 
BEGIN
   ASSERT b4' DELAYED'STABLE (5 ns)
      REPORT "Error occured!"
      SEVERITY Error;
   passive_procedure(b2,delay);
END big_example ;