synthesizeable_vhdl-model-library:patras:special

SPECIAL COMPONENTS library

The SPECIAL COMPONENTS library consists of the following 6 generic components:

  • bcd_ss: BCD to Seven-Segment encoder
  • hex_ss: HEX to Seven-Segment encoder
  • nrz_hdb3: NRZ to HDB3 encoder (NRZ : Non-Return to Zero, HDB3 : High Density Bipolar 3)
  • hdb3_nrz: HDB3 to NRZ encoder (NRZ : Non-Return to Zero, HDB3 : High Density Bipolar 3)
  • bcdN_bin: N-digits BCD to binary converter with error flag in conversion
  • bin_bcdN: Binary to N-digits BCD converter with error flag in conversion

The SPECIAL COMPONENTS library can be verified with this testbench: test_special

special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    bcd_ss : BCD to Seven-Segment encoder.                   #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- bcd_ss Entity Description
entity bcd_ss is
   port(
      Din: in unsigned(3 downto 0);
      EN, L: in std_ulogic;
      a, b, c, d, e, f, g: out std_ulogic
--------------------
--                --
--       a        --
--    f |-| b     --
--  e,g |-| c     --
--       -        --
--       d        --
--                --
--------------------
   );
end bcd_ss;
 
-- bcd_ss Architecture Description
architecture rtl of bcd_ss is
signal l_d: unsigned(3 downto 0) :="0000";
signal error : std_ulogic;
begin
Decoder_Process: process (Din, l_d, EN, L)
begin
if L='1' then
	l_d<=Din;
end if;
end process Decoder_Process;
 
error <= '1' WHEN (l_d>="1010" or EN='0') ELSE '0';
 
a <= '0' WHEN (l_d="0001" or l_d="0100" or error='1') ELSE '1'; 
b <= '0' WHEN (l_d="0101" or l_d="0110" or error='1') ELSE '1'; 
c <= '0' WHEN (l_d="0010" or error='1')               ELSE '1'; 
d <= '0' WHEN (l_d="0001" or l_d="0100" or l_d="0111" or 
               error='1')                             ELSE '1'; 
e <= '0' WHEN (l_d="0001" or l_d="0011" or l_d="0100" or 
               l_d="0101" or l_d="0111" or l_d="1001" or 
               error='1')                             ELSE '1'; 
f <= '0' WHEN (l_d="0001" or l_d="0010" or l_d="0011" or 
               l_d="0111" or error='1')               ELSE '1'; 
g <= '0' WHEN (l_d="0000" or l_d="0001" or l_d="0111" or 
               error='1')                             ELSE '1'; 
end rtl;
special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    hex_ss : HEX to Seven Segment encoder.                   #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- hex_ss Entity Description
entity hex_ss is
   port(
      Din: in unsigned(3 downto 0);
      EN, L: in std_ulogic;
      a, b, c, d, e, f, g: out std_ulogic
 
--------------------
--                --
--       a        --
--    f |-| b     --
--  e,g |-| c     --
--       -        --
--       d        --
--                --
--------------------
 
   );
end hex_ss;
 
-- hex_ss Architecture Description
architecture rtl of hex_ss is
signal l_d: unsigned(3 downto 0) :="0000";
signal error : std_ulogic;
begin
 
Decoder_Process: process (Din, l_d, EN, L)
begin
if L='1' then
	l_d<=Din;
end if;
end process Decoder_Process;
 
error <= not EN; 
 
a <=  '0' WHEN (l_d="0001" or l_d="0100" or l_d="1011" or 
		l_d="1101" or error='1')                             ELSE '1';
b <=  '0' WHEN (l_d="0101" or l_d="0110" or l_d="1011" or 
		l_d="1100" or l_d="1110" or l_d="1111" or error='1') ELSE '1';
c <=  '0' WHEN (l_d="0010" or l_d="1100" or l_d="1110" or 
		l_d="1111" or error='1')                             ELSE '1';
d <=  '0' WHEN (l_d="0001" or l_d="0100" or l_d="0111" or 
                l_d="1001" or l_d="1010" or l_d="1111" or error='1') ELSE '1';
e <=  '0' WHEN (l_d="0001" or l_d="0011" or l_d="0100" or 
                l_d="0101" or l_d="0111" or l_d="1001" or error='1') ELSE '1';
f <=  '0' WHEN (l_d="0001" or l_d="0010" or l_d="0011" or 
                l_d="0111" or l_d="1101" or error='1')               ELSE '1'; 
g <=  '0' WHEN (l_d="0000" or l_d="0001" or l_d="0111" or 
		l_d="1100" or error='1')                             ELSE '1';
end rtl;
special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    nrz_hdb3 : NRZ to HDB3 encoder (NRZ : Non-Return to Zero,#
-- #                            HDB3 : High Density Bipolar 3).               #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- nrz_hdb3 Entity Description
entity nrz_hdb3 is
	port(
		RES, CLK, NRZ: in std_ulogic;
		POS, NEG: out std_ulogic
	);
end nrz_hdb3;
 
-- nrz_hdb3 Architecture Description
architecture rtl of nrz_hdb3 is
	signal q: unsigned(3 downto 0);	
	signal zero, vl, ch, pos_neg, qzh: std_ulogic;
 
begin
	ch<=vl xor pos_neg;
	zero<=not(q(3) or q(2) or q(1) or q(0));
	qzh<=q(3) or (zero and ch);
 
	POS<=CLK and pos_neg and qzh;
	NEG<=CLK and not(pos_neg) and qzh;
 
	NRZ_Process:process(CLK, RES)
	begin
		if (RES='0') then
			q<=(OTHERS=>'0');
		   vl<='0';
			pos_neg<='1';
		elsif (rising_edge(CLK)) then
			q(0)<=NRZ;
			q(1)<=(q(0) or zero);
			q(3 downto 2)<=q(2 downto 1);
			if (zero='1') then
				vl<=not(vl);
			end if;
			if(((zero and (not(ch))) or q(3)) = '1') then
				pos_neg<=not(pos_neg);
			end if;
		end if;
	end process NRZ_Process;
end rtl;
special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    hdb3_nrz : HDB3 to NRZ encoder.                          #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- hdb3_nrz Entity Description
entity hdb3_nrz is
	port(
		RES, CLK, POS, NEG: in std_ulogic;
		NRZ, ERR: out std_ulogic
	);
end hdb3_nrz;
 
-- hdb3_nrz Architecture Description
architecture rtl of hdb3_nrz is
	signal s: unsigned(2 downto 0);	
	signal o_pos, o_neg, q, vln: std_ulogic;
 
begin
	vln<=((o_pos and q) or (o_neg and (not(q))));
	NRZ<=(s(2) and (not(vln)));
	ERR<=(((not(s(0))) and (not(s(1))) and vln) or (not(vln)));
 
	HDB3_Process:process(CLK, RES)
	begin
		if (RES='0') then
			s<=(OTHERS=>'0');
		   o_pos<='0';
			o_neg<='0';
			q<='0';
		elsif (rising_edge(CLK)) then
			o_pos<=POS;
			o_neg<=NEG;
			s(0)<=((o_pos or o_neg) and (not(vln)));
			s(2 downto 1)<=s(1 downto 0);
			q<=(o_pos or (q and (not(o_neg))));
		end if;
	end process HDB3_Process;
end rtl;
special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    bcdX_bin : X-digits BCD to binary converter with         #
-- #                            error output.                                 #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
ENTITY bcdX_bin IS
	GENERIC(X : integer := 2);
	PORT(
		D: IN unsigned((3*X+1) DOWNTO 0);
		Q: OUT unsigned((4*X-1) DOWNTO 0);
		E: OUT std_ulogic
	);
END bcdX_bin;
 
-- bcNx_bin Architecture Description
ARCHITECTURE rtl OF bcdx_bin IS
	CONSTANT N: integer :=4*X; -- width of D in bits
	CONSTANT M: integer :=X; -- width of D in bcd digits
BEGIN
	Convert_Process:process(D)
		VARIABLE p: unsigned(N+3 DOWNTO 0);
		VARIABLE error: std_ulogic:='0';
	BEGIN
		p:=Conv_Unsigned(0, N) & D(N-1 DOWNTO N-4);
		error:='0';
		if (D(N-1 DOWNTO N-4)>="1010") then
			error:='1';
                END if;
		FOR i IN M-2 DOWNTO 0 loop
			if (d((i*4)+3 downto i*4)>"1010") then
				error:='1';
                        END if;
			p:=p(N-1 downto 0) * "1010" + 
                        Conv_Unsigned(Conv_Integer(('0' & d((i*4)+3 DOWNTO (i*4))),0),N+4);
		END loop;
		Q<=p(N-1 downto 0);
		E<=error;
	END process Convert_Process;
END rtl;
special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    bin_bcdX : Binary to X-digits BCD converter with         #
-- #                            error output.                                 #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
 
-- bin_bcdX Entity Description
ENTITY bin_bcdX IS
	GENERIC(X : integer := 2);
	PORT(
		D: IN unsigned((4*X-1) DOWNTO 0);
		Q: OUT unsigned((3*X+1) DOWNTO 0);
		E: OUT std_ulogic
	);
end bin_bcdx;
 
-- bin_bcdx Architecture Description
ARCHITECTURE rtl OF bin_bcdX IS
    CONSTANT N: integer :=3*X+2; -- length of input in bits
    CONSTANT M: integer :=X;  -- length of output in BCD digits
BEGIN
    Convert_Process:process(D)
	VARIABLE r: unsigned(N+3 DOWNTO 0);
    BEGIN
	r:=(OTHERS=>'0');
	IF D(N-1 DOWNTO N-3)>"100" THEN
		r(3 DOWNTO 0):=('0' & D(N-1 DOWNTO N-3)) + "0011";
	ELSE
		r(3 DOWNTO 0):='0' & D(N-1 DOWNTO N-3);
	END IF;
	FOR i IN 0 TO N-5 loop
		r:=r(r'LEFT-1 DOWNTO 0) & D(N-4-i);
		FOR j IN 0 TO M-1 loop
			IF j*3<i+2 THEN
				IF r((j*4)+3 DOWNTO j*4)>"0100" THEN
					r((j*4)+3 DOWNTO j*4):=r((j*4)+3 DOWNTO j*4) + "0011";
				END IF;
			END IF;
		END loop; 
	END loop;
	r:=r(r'LEFT-1 DOWNTO 0) & D(0);
	Q<=r((4*M)-1 DOWNTO 0);
	IF Conv_Integer(r(r'LEFT DOWNTO 4*M),0)/=0 THEN
		E<='1';
	ELSE
		E<='0';
	END IF;
    END PROCESS Convert_Process;
END rtl;
test_special.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_special.vhd                                         #
-- #                                                                          #
-- # Component  :    test_special : Test bench for various special components.#
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.ALL;
 
ENTITY test_special IS
END test_special;
 
 
ARCHITECTURE rtl OF test_special IS
 
 COMPONENT dec_2
	GENERIC(x : INTEGER := 2);
	PORT(
		D: IN unsigned((3*x+1) DOWNTO 0);
		Q: OUT unsigned((4*x-1) DOWNTO 0);
		E: OUT std_ulogic
	);
 END COMPONENT;
 
 COMPONENT dec_1
	GENERIC(x : INTEGER := 2);
	PORT(
		D: IN unsigned((4*x-1) DOWNTO 0);
		Q: OUT unsigned((3*x+1) DOWNTO 0);
		E: OUT std_ulogic
	);
 END COMPONENT;
 
 FOR dec1 : dec_1 USE ENTITY WORK.bcdx_bin(rtl);
 FOR dec2 : dec_2 USE ENTITY WORK.bin_bcdx(rtl);
 
 SIGNAL bcd_input : unsigned (7 DOWNTO 0); 
 SIGNAL bcd_output : unsigned (7 DOWNTO 0); 
 SIGNAL bin_output : unsigned (7 DOWNTO 0);
 SIGNAL error1 : std_ulogic;
 SIGNAL error2 : std_ulogic;
 
 BEGIN
  dec1: dec_1
	GENERIC MAP(x => 2)
	PORT MAP(
		D => bcd_input,
		Q => bin_output,
		E => error1);
 
 dec2: dec_2
	GENERIC MAP(x => 2)
	PORT MAP (
		D => bin_output,
		Q => bcd_output,
		E => error2);
 
	bcd_input <=	"01010001" AFTER 100 ns, 
			"00010101" AFTER 200 ns,
			"11010001" AFTER 300 ns,
			"00000001" AFTER 400 ns;
 
END rtl;