-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    hdb3_nrz : HDB3 to NRZ encoder.                          #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

-- hdb3_nrz Entity Description
entity hdb3_nrz is
	port(
		RES, CLK, POS, NEG: in std_ulogic;
		NRZ, ERR: out std_ulogic
	);
end hdb3_nrz;

-- hdb3_nrz Architecture Description
architecture rtl of hdb3_nrz is
	signal s: unsigned(2 downto 0);	
	signal o_pos, o_neg, q, vln: std_ulogic;
	
begin
	vln<=((o_pos and q) or (o_neg and (not(q))));
	NRZ<=(s(2) and (not(vln)));
	ERR<=(((not(s(0))) and (not(s(1))) and vln) or (not(vln)));

	HDB3_Process:process(CLK, RES)
	begin
		if (RES='0') then
			s<=(OTHERS=>'0');
		   o_pos<='0';
			o_neg<='0';
			q<='0';
		elsif (rising_edge(CLK)) then
			o_pos<=POS;
			o_neg<=NEG;
			s(0)<=((o_pos or o_neg) and (not(vln)));
			s(2 downto 1)<=s(1 downto 0);
			q<=(o_pos or (q and (not(o_neg))));
		end if;
	end process HDB3_Process;
end rtl;