-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    special.vhd                                              #
-- #                                                                          #
-- # Component  :    nrz_hdb3 : NRZ to HDB3 encoder (NRZ : Non-Return to Zero,#
-- #                            HDB3 : High Density Bipolar 3).               #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

-- nrz_hdb3 Entity Description
entity nrz_hdb3 is
	port(
		RES, CLK, NRZ: in std_ulogic;
		POS, NEG: out std_ulogic
	);
end nrz_hdb3;

-- nrz_hdb3 Architecture Description
architecture rtl of nrz_hdb3 is
	signal q: unsigned(3 downto 0);	
	signal zero, vl, ch, pos_neg, qzh: std_ulogic;
	
begin
	ch<=vl xor pos_neg;
	zero<=not(q(3) or q(2) or q(1) or q(0));
	qzh<=q(3) or (zero and ch);
	
	POS<=CLK and pos_neg and qzh;
	NEG<=CLK and not(pos_neg) and qzh;

	NRZ_Process:process(CLK, RES)
	begin
		if (RES='0') then
			q<=(OTHERS=>'0');
		   vl<='0';
			pos_neg<='1';
		elsif (rising_edge(CLK)) then
			q(0)<=NRZ;
			q(1)<=(q(0) or zero);
			q(3 downto 2)<=q(2 downto 1);
			if (zero='1') then
				vl<=not(vl);
			end if;
			if(((zero and (not(ch))) or q(3)) = '1') then
				pos_neg<=not(pos_neg);
			end if;
		end if;
	end process NRZ_Process;
end rtl;