-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : special.vhd # -- # # -- # Component : bcdX_bin : X-digits BCD to binary converter with # -- # error output. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; ENTITY bcdX_bin IS GENERIC(X : integer := 2); PORT( D: IN unsigned((3*X+1) DOWNTO 0); Q: OUT unsigned((4*X-1) DOWNTO 0); E: OUT std_ulogic ); END bcdX_bin; -- bcNx_bin Architecture Description ARCHITECTURE rtl OF bcdx_bin IS CONSTANT N: integer :=4*X; -- width of D in bits CONSTANT M: integer :=X; -- width of D in bcd digits BEGIN Convert_Process:process(D) VARIABLE p: unsigned(N+3 DOWNTO 0); VARIABLE error: std_ulogic:='0'; BEGIN p:=Conv_Unsigned(0, N) & D(N-1 DOWNTO N-4); error:='0'; if (D(N-1 DOWNTO N-4)>="1010") then error:='1'; END if; FOR i IN M-2 DOWNTO 0 loop if (d((i*4)+3 downto i*4)>"1010") then error:='1'; END if; p:=p(N-1 downto 0) * "1010" + Conv_Unsigned(Conv_Integer(('0' & d((i*4)+3 DOWNTO (i*4))),0),N+4); END loop; Q<=p(N-1 downto 0); E<=error; END process Convert_Process; END rtl;