-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_special.vhd # -- # # -- # Component : test_special : Test bench for various special components.# -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.ALL; ENTITY test_special IS END test_special; ARCHITECTURE rtl OF test_special IS COMPONENT dec_2 GENERIC(x : INTEGER := 2); PORT( D: IN unsigned((3*x+1) DOWNTO 0); Q: OUT unsigned((4*x-1) DOWNTO 0); E: OUT std_ulogic ); END COMPONENT; COMPONENT dec_1 GENERIC(x : INTEGER := 2); PORT( D: IN unsigned((4*x-1) DOWNTO 0); Q: OUT unsigned((3*x+1) DOWNTO 0); E: OUT std_ulogic ); END COMPONENT; FOR dec1 : dec_1 USE ENTITY WORK.bcdx_bin(rtl); FOR dec2 : dec_2 USE ENTITY WORK.bin_bcdx(rtl); SIGNAL bcd_input : unsigned (7 DOWNTO 0); SIGNAL bcd_output : unsigned (7 DOWNTO 0); SIGNAL bin_output : unsigned (7 DOWNTO 0); SIGNAL error1 : std_ulogic; SIGNAL error2 : std_ulogic; BEGIN dec1: dec_1 GENERIC MAP(x => 2) PORT MAP( D => bcd_input, Q => bin_output, E => error1); dec2: dec_2 GENERIC MAP(x => 2) PORT MAP ( D => bin_output, Q => bcd_output, E => error2); bcd_input <= "01010001" AFTER 100 ns, "00010101" AFTER 200 ns, "11010001" AFTER 300 ns, "00000001" AFTER 400 ns; END rtl;