-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : special.vhd # -- # # -- # Component : bin_bcdX : Binary to X-digits BCD converter with # -- # error output. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- bin_bcdX Entity Description ENTITY bin_bcdX IS GENERIC(X : integer := 2); PORT( D: IN unsigned((4*X-1) DOWNTO 0); Q: OUT unsigned((3*X+1) DOWNTO 0); E: OUT std_ulogic ); end bin_bcdx; -- bin_bcdx Architecture Description ARCHITECTURE rtl OF bin_bcdX IS CONSTANT N: integer :=3*X+2; -- length of input in bits CONSTANT M: integer :=X; -- length of output in BCD digits BEGIN Convert_Process:process(D) VARIABLE r: unsigned(N+3 DOWNTO 0); BEGIN r:=(OTHERS=>'0'); IF D(N-1 DOWNTO N-3)>"100" THEN r(3 DOWNTO 0):=('0' & D(N-1 DOWNTO N-3)) + "0011"; ELSE r(3 DOWNTO 0):='0' & D(N-1 DOWNTO N-3); END IF; FOR i IN 0 TO N-5 loop r:=r(r'LEFT-1 DOWNTO 0) & D(N-4-i); FOR j IN 0 TO M-1 loop IF j*3"0100" THEN r((j*4)+3 DOWNTO j*4):=r((j*4)+3 DOWNTO j*4) + "0011"; END IF; END IF; END loop; END loop; r:=r(r'LEFT-1 DOWNTO 0) & D(0); Q<=r((4*M)-1 DOWNTO 0); IF Conv_Integer(r(r'LEFT DOWNTO 4*M),0)/=0 THEN E<='1'; ELSE E<='0'; END IF; END PROCESS Convert_Process; END rtl;