VHDL Tutorial

The tutorial describes the concept of VHDL for modeling and synthesis. Short examples explain the difference between a normal sequential programming language and the concurrent VHDL methodology. The main language constructs are described. The difference in use of VHDL for simulation and for synthesis is pointed out.

We clarify how readable and synthezisable code should be structured, what language constructs should be avoided and how packages should be managed. We describe the use of VHDL to generate sequential and combinational circuits and to avoid the generation of latches. The issues mentioned are worked on in the VHDL workshop.