-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : special.vhd # -- # # -- # Component : bcd_ss : BCD to Seven-Segment encoder. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- bcd_ss Entity Description entity bcd_ss is port( Din: in unsigned(3 downto 0); EN, L: in std_ulogic; a, b, c, d, e, f, g: out std_ulogic -------------------- -- -- -- a -- -- f |-| b -- -- e,g |-| c -- -- - -- -- d -- -- -- -------------------- ); end bcd_ss; -- bcd_ss Architecture Description architecture rtl of bcd_ss is signal l_d: unsigned(3 downto 0) :="0000"; signal error : std_ulogic; begin Decoder_Process: process (Din, l_d, EN, L) begin if L='1' then l_d<=Din; end if; end process Decoder_Process; error <= '1' WHEN (l_d>="1010" or EN='0') ELSE '0'; a <= '0' WHEN (l_d="0001" or l_d="0100" or error='1') ELSE '1'; b <= '0' WHEN (l_d="0101" or l_d="0110" or error='1') ELSE '1'; c <= '0' WHEN (l_d="0010" or error='1') ELSE '1'; d <= '0' WHEN (l_d="0001" or l_d="0100" or l_d="0111" or error='1') ELSE '1'; e <= '0' WHEN (l_d="0001" or l_d="0011" or l_d="0100" or l_d="0101" or l_d="0111" or l_d="1001" or error='1') ELSE '1'; f <= '0' WHEN (l_d="0001" or l_d="0010" or l_d="0011" or l_d="0111" or error='1') ELSE '1'; g <= '0' WHEN (l_d="0000" or l_d="0001" or l_d="0111" or error='1') ELSE '1'; end rtl;