Finite State Machines and VHDL
Introduction
- FSM (Finite State Machine) Types
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- The output vector (Y) resembles the state vector (S): Y = S
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- The output vector (Y) is a function of the state vector (S): Y = f(S)
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- The output vector (Y) is a function of state vector (S) and the input vector (X): Y = f(X,S)
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Notes
In this chapter, the different types of finite state machines, their graphical representation and ways to model them with VHDL will be shown.
Furthermore only synchronous automatons are assumed.
Generally every finite state machine can be described either by one single or by two separated processes. Implementation guidelines and advantages or drawbacks of the different variants will be given.
The actual states of a state machine should generally be described by descriptive names.
This can be achieved by use of an enumeration type whose values are these names. Later in the synthesis process, these names have to be mapped to a binary representation. This step is called state encoding.
There are several versions of finite state machines. The standard versions known in theory are Medvedev, Moore and Mealy machines. However, there are far more versions than these three.
It is for example recommended for several reasons to place storing elements (registers, Flip Flops) at the module outputs. By doing this, additional versions of finite state machines can be build, which will be shown later.
Chapters of System Design > Synthesis > Finite State Machines and VHDL