FSM and Synthesis
Fundamentals
- Many constraints imaginable for synthesis
- Mostly used constraints:
- Speed → clock period
- Area → maximum area set to 0
- Power → maximum power allowed
- Operating environments
- Port attributes
- Constraints for FSM:
- Clock period
- FSM optimization (extraction) → not often because less success
- FlipFlop and latch attributes
FlipFlop and Latch Attributes
- FlipFlop types:
- FSM with two state processes: Usually results in D-FlipFlops
- FSM with one state process: Usually results in JK-FlipFlops
- Speed and area constraints lead not necessarily to a specifically FlipFlop type
- Have to set default FlipFlop type:
- Only the family (D, JK or other)
- Exact FlipFlop type to use (exact type name)
State Processes and Synthesis
- Normally better synthesis results for two state processes
- Example: Mealy FSM
Optimization | Default | Area | Speed | |||
---|---|---|---|---|---|---|
# of Processes \ report | Area | Speed | Area | Speed | Area | Speed |
One (JK FlipFlops) | 52 GE | 4.89 ns | 51 GE | 4.89 ns | 60 GE | 3.90 ns |
One (D FlipFlops) | 39 GE | 5.28 ns | 38 GE | 5.12 ns | 49 GE | 4.77 ns |
Two | 41 GE | 5.24 ns | 39 GE | 4.83 ns | 52 GE | 3.78 ns |
Chapters of System Design > Synthesis > Finite State Machines and VHDL