What is Synthesis?

Notes

In general, the term “synthesis” is used for the automated transformation of RT level descriptions into gate level representations. This transformation is mainly influenced by the set of basic cells that is available in the target technology. While simple operations like comparisons and either/or decisions are easily mapped to boolean functions, more complex constructs like mathematical operators are mapped to a tool specific macro cell library first.

This means that a number of adder, multiplier, etc. architectures are known to the synthesis tool and these designs are treated as if they were designed by the user.

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The macro cell library is just one distinguishing feature of synthesis software. VHDL itself is not fully synthesizable and the available tools differ in the language subset that is supported. Complex user defined data structures like records and multidimensional arrays (e.g. simple arrays of integers) turn out to be the most problematic cases.

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The consequences of different language support on the resulting hardware are demonstrated at the example of a clocked process. In case the synthesis tool supports sensitivity lists the result is a flip flop because the process is triggered with every event at CLK and the value of D will be assigned to Q, if CLK=’1’ as a result of this event. Thus, the behavior of a rising edge triggered flip flop is modelled here.

Even if synthesis tools do not support sensitivity lists in general, they often look for templates that describe the behavior of registers. Usually, the check for the CLK event has to be part of the if condition, as well. If the sensitivity list is ignored and the code can not be matched to a register template, a level triggered latch will be generated!

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Besides the fixed synthesis constraints set by the target technology and the tool capabilities, “soft” constraints that are imposed by the designer have to be considered as well. Maximum operating speed and required hardware resources are usually the main targets for netlist optimization. This is possible either on a purely abstract mathematical model or by different mappings of the boolean functions on the available technology cells. Due to the complexity, the optimization phase requires quite a lot of iterations before the software reports its final result.

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Even after extensive optimizations by the synthesis tool, the result is pretty often not compliant with the system requirements. In this case, the input to the software has to be modified. Several parameters may be modified by the designer: The block operating conditions includes environmental conditions like operating temperature as well as settings like necessary driver strength (fan-out) or capacitance of wire connections. They have a direct impact on the actual wire delays.

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Hierarchy alterations can simply be performed by selecting a bigger block and allowing the tool to break up the hierarchy definitions from the VHDL source code. If the repeated attempts still fail to produce the desired result, modifications of the original VHDL code become the last way out.

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There exist still a number of problems and pitfalls for the users of synthesis tools.

Many issues are related to the separation of netlist and layout generation.

Therefore the length of the interconnections can only be estimated during synthesis and critical nets have to modified by hand afterwards.

The clock tree, for example, requires extensive buffering in order to distribute the clock signal evenly on the chip and has to be generated by hand.

While synthesis of synchronous designs with a single clock source is fairly simple, practical systems, unfortunately, often require additional clock signals.

This introduces asynchronous behavior which is very complex to handle as long as the exact propagation delays are unknown.

Macro cells that are available in the target technology are also hard to use.

This is especially true for memory cells that can not used by synthesis tools automatically. The same applies to the I/O cells of ASIC libraries that have to chosen by hand.

Notes

The VHDL coding style itself has a rather big impact on the synthesis result.

Therefore it is necessary to keep this in mind even if the model is to be synthesized at the last step of the development cycle.

The design partitioning should be reviewed prior to the synthesis runs. This is mainly due to the fact that the algorithms perform best at module sizes of several thousand gates.

It is not necessary to rewrite the RTL description as submodules can be grouped together during synthesis. This allows for different optimization settings, i.e. high speed parts can be synthesized with very stringent timing constraints while non critical parts should consume the least amount of resources (area) possible.