courses:system_design:synthesis:finite_state_machines_and_vhdl:fsm_and_simulation

FSM and Simulation

Fundamentals

  • Simulation cycle consists of two phases
    • Signal update phase
    • Process execution phase

Simulytion Cycle

  • Combinational processes:
    • Signal update at any time
    • Process execution with new values and signal updates until no process execution necessary anymore
  • Clocked processes:
    • Signal update of CLOCK SIGNAL
    • Process execution with currently (old) values of inputs and following (combinational) process executions.
  • What if clock and inputs change at the same time?

Clocked Process Simulation (1)

  • FSM is fed with outputs from other registers

FSM is fed with outputs from other registers

  • X changes only after clock edge
  • STATE signal renewed before X changes ⇒ STATE takes over old value of NEXTSTATE
  • STATE = F( STATEold, Xold)

Clocked Process Simulation (2)

  • FSM is fed with asynchronous inputs (X); TWO state processes

FSM is fed with asynchronous inputs

  • X can change together with clock edge
  • Physical world: STATE signal renewed before NEXTSTATE changes
RTL-Simulation: Updaten Updaten+1 STATE
CLK, … X, … F(STATEold, Xold)
CLK, X, … … F(STATEold, Xold)
X, … CLK, … F(STATEold, Xnew)

Clocked Process Simulation (3)

  • FSM is fed with asynchronous inputs (X); ONE state process

FSM is fed with asynchronous inputs

  • X can change together with clock edge
  • Physical world: STATE signal renewed before NEXTSTATE changes
RTL-Simulation: Updaten Updaten+1 STATE
CLK, … X, … F(STATEold, Xold)
CLK, X, … … F(STATEold, Xnew)
X, … CLK, … F(STATEold, Xnew)

Recommodations for Simulation

  • Don't assign stimulis together with clock edge
  • Use two state processes
  • Use concurrent signal assignments for clock generation (⇒ will be updated in prior Δ-Cycles than processes)
CLK <= not CLK after PERIOD/2 ;
 
process begin
    CLK <= not CLK ;
    wait for PERIOD/2 ;
end process ;
Δm,n ⇒ CLK in update list for Δm+i,1
Δm+i,1 ⇒ CLK update 		Δm,n ⇒ CLK update (because of wait …)
Δm+i,1 ⇒ Update of signals in update list ⇒ Process execution
Δm+i,2 ⇒ CLK update

Chapters of System Design > Synthesis > Finite State Machines and VHDL

Chapters of System Design > Synthesis