Synthesizeable VHDL-Model-Library

We have implemented parameterizeable VHDL models and Testbenches. You type in the portwidth and receive the synthesizeable VHDL description (and the accordingly testbench and a trace file for the SYNOPSYS VHDL-simulator).

Here you find our package with specifc types.



University of Patras
Dept. of Electrical and Computer Engineering
Prof. Ph.D. C. Goutis
Patras, 26110 Greece
Tel.: +30-61-997340
Fax: +30-61-994798


The modules are implemented as parameterizeable VHDL models and Testbenches. By selecting the corresponding link you receive the VHDL description of the module or the testbench. After marking the VHDL source code and copying it to a local text file, you just have to insert the appropriate values for the generics in the entities or component instantiations.

Here you find a package with useful functions.


  • ALUs: Various Arithmetic and Logical Units
  • COMPARATORs: Equality and Magnitude Comparators
  • COUNTERs: Up-Down, Binary-Gray Counters
  • ENCODERs_DECODERs: Encoders and Decoders
  • FIFOs: Single and Dual Clocked FIFOS
  • INCREMENTERs_DECREMENTERs: Incrementers and Decrementers
  • MUXERs: Various width Multiplexers
  • REGISTERs: Register Files
  • SHIFTERs: Left, Right and Bidirectional Shifters with various Input-Output Options
  • SPECIAL: Various Models that Perform special functions
  • UNIVERSAL MULTIPLIER: A universal multiplier that implements the multiplication in all arithmetic number systems (i.e. unsigned.signed-magnitude, 1's complement and 2's complement)
  • FIR: An unrolled implementation of an FIR (Finite Impulse Response) filter. The multiplications are implemented using shift-add operations.