courses:system_design:vhdl_language_and_syntax:extended_data_types:enumeration_types

Enumeration Types

Syntax

architecture EXAMPLE of ENUMERATION is
 
 type T_STATE is
      (RESET, START, EXECUTE, FINISH);
 
  signal CURRENT_STATE : T_STATE;
  signal NEXT_STATE    : T_STATE;
  signal TWO_BIT_VEC : bit_vector(1 downto 0);
 
begin
 
 -- valid signal assignments
  NEXT_STATE    <= CURRENT_STATE;
  CURRENT_STATE <= RESET;
 
 -- invalid signal assignments
  CURRENT_STATE <= "00";
  CURRENT_STATE <= TWO_BIT_VEC;
 
end EXAMPLE;
  • Designer may define their own types
    • Enhanced readability (commonly used to descibe the states of a state machine)
    • Limited legal values
Synthesis tools map enumerations onto a suitable bit pattern automatically

Notes

It is possible to define new scalar data types in VHDL. They are called enumeration types because all possible object (constant, signal, variable) values have to be specified in a list at type declaration. User defined data types are frequently used to enhance readability when dealing with so called state machines, i.e. modules that behave differently, depending on the state of internal storage elements. Instead of fixed bit patterns, the symbolic names of the data type values are used which will be mapped to a bit level representation automatically during synthesis.

In the example, a new data type with values denoting four different states (RESET, START, EXECUTE, FINISH) is defined. This type is used for the two signals CURRENT_STATE and NEXT_STATE and the four declared type values can be assigned directly. Of course, after synthesis, there will be two bits for each signal, but a direct assignment of a two bit vector is not allowed. In a signal assignment only those values may be used which are enumerated in the type declaration.

Some synthesis tools allow the designer to map the different values onto specific bit patterns.

Enumeration Types - Example

architecture RTL of TRAFFIC_LIGHT is
  type T_STATE is
    (INIT,RED,REDYELLOW,GREEN,YELLOW);
  signal STATE, NEXT_STATE : T_STATE;
 
  signal COUNTER: integer;
  constant END_RED   : integer := 10000;
  constant END_GREEN : integer := 20000;
 
begin
  LOGIC : process (STATE, COUNTER)
  begin
    NEXT_STATE <= STATE;
      case STATE is
         when RED =>
           if COUNTER = END_RED then
             NEXT_STATE <= REDYELLOW;
           end if;
         when REDYELLOW => -- statements
         when GREEN     => -- statements
         when YELLOW    => -- statements
         when INIT      => -- statements
   end case;
  end process LOGIC;
end RTL;

Enumeration Types

Notes

The example demonstrates the impact of user defined data types on code readability. The LOGIC block shall implement the behavior of a traffic light controller. The data type T_STATE is defined in the declarative part of the architecture and is used for the signals STATE and NEXT_STATE. The functional behavior of the algorithm should be pretty obvious as symbolic names are used, only. For this purpose, additional constants were defined for the specific counter values that are checked within the code.

Chapters of System Design > VHDL Language and Syntax > Extended Data Types

Chapters of System Design > VHDL Language and Syntax