Standard Logic Type

Notes

The ’bit’ type has only the two values ’0’ and ’1’. While this is enough to model simple logic where the wires are driven either high or low level, further options are desirable, especially for simulation purposes. VHDL objects are initialised with their default value which is the leftmost value from the type declaration. Therefore, every variable/signal of type ’bit’ would be set to ’0’ at the beginning of each simulation. This makes it impossible to verify the proper reset behavior of a design, if the reset value of a register is also ’0’.

Notes

Additional legal wire conditions are necessary, if different driver strengths or high impedance outputs of real hardware drivers are to be modelled. It depends on the synthesis tool whether these additional logic values can be mapped to the corresponding hardware cells. In order to avoid hardware overhead one might think of designating bit positions that may safely be ignored during synthesis (“don’t care”).

For simulation, the opposite is desirable, i.e. a value which indicates that something went wrong and needs to be inspected (“undefined”). In the beginning, several incompatible multi- valued logic systems were defined by the different software companies. In order to solve the resulting problems, a standardized 9-valued logic system was defined and accepted by the IEEE in 1992.

Notes

The new data type is called ’std_ulogic’ and is defined in the package ’std_logic_1164’ which is placed in the library IEEE (i.e. it is included by the following statement: ’use IEEE.std_logic_1164.all’). The new type is implemented as enumerated type by extending the existing ’0’ and ’1’ symbols with additional ASCII characters. The most important ones are probably ’u’ (uninitialized) and ’x’ (unknown value). The ’u’ symbol is the leftmost symbol of the declaration, i.e. it will be used as initial value during simulation.

Notes

Besides the type definition of ’std_ulogic’ the ’std_logic_1164’ package contains also the definition of a similar type called ’std_logic’ which has the same value set as ’std_ulogic’. Like ’bit_vector’, array data types ’std_(u)logic_vector’ are also available. Additionally, all operators that are defined for the standard type ’bit’ are overloaded to handle the new replacement type.

As mentioned before, the ’bit’ data type can not be used to model bus architectures. This is because all signal assignments are represented by drivers in VHDL. If more than one driver try to force the value of a signal a resolution will be needed to solve the conflict. Consequently, the existence of a resolution function is necessary for legal signal assignments. Please note, resolution conflicts are detected at run-time and not during compilation! Predefined VHDL data types do not possess a resolution function because the effects of multiple signal drivers depend on the actual hardware realization.

Notes

The ’std_ulogic’ data type (“u” = “unresolved”) is the basis for the resolved data type’std_logic’.

The ’resolved’ function that is also defined in the ’std_logic_1164’ package gets called whenever signal assignments involving ’std_logic’ based data types are carried out.

Notes

The conflict resolution process itself, i.e. the decision about the final signal value in case of multiple drivers, is based upon a resolution table. All driving values are collected in an array and handed to the resolution function, even if only a single driver is present! The result is calculated element by element: the current result selects the row of the resolution table and the value of the next signal driver selects the column of the resulting signal value.

Notes

By far most of the connections in a design, either as abstract signals or later on as real wires, are from one point to another, i.e. multiple signal drivers would indicate an error. This kind of error will be easily detected if just unresolved data types are used.

Yet, the resolved counterpart ’std_logic’ has been established as de facto industry standard despite of some shortcomings. As all kind of hardware structures, including bus systems, can be modelled with this data type it is used by synthesis tools for the resulting gate level description of a design. Even a workaround exists, so that multiple signal assignments can still be detected: the port mode ’buffer’ allows for a single signal driver, only. According to the VHDL language definition, however, the resolution function has to be called when resolved signals are assigned. The impact on simulation performance depends on the compiler/ simulator implementation.

The last, but certainly not the least advantage of ’std_logic’ based designs is the existence of standard packages defining arithmetical operations on vectors. This eliminates the need for complex type conversion functions and thus enhances the readability of the code.

Notes

The 'numeric_std' package is located in the library IEEE and provides two numerical interpretations of the bit vector, either as signed or as unsigned integer value. Overloaded operators to mix vectors and integers in expressions are also available.

Please note, that it is impossible to overload the signal assignment operator, i.e. a function must be called in this case. Conversion functions 'to_integer' and 'to_(un)signed' are also defined in the package.

The equivalent of 'numeric_std' for 'bit' based operations is called 'numeric_bit'. The use of 'bit' based signals is not recommended, however, due to the disadvantages of a 2-valued logic system.