Concurrent Statements

Concurrent statements are executed at the same time;
independent of the order in which they appear

Notes

All statements within architectures are executed concurrently.

While it is possible to use VHDL processes as the only concurrent statement, the necessary overhead (process, begin, end, sensitivity list) lets designer look for alternatives when the sequential behavior of processes is not needed.

The signal assignment statement:

The signal on the left side of the assignment operator ’⇐’ receives a new value whenever a signal on the right side changes.
The new value stems from another signal or can be calculated from a number of other signals.

TARGET <= VALUE;
 
TARGET <= VALUE_1 when CONDITION_1 else
          VALUE_2 when CONDITION_2 else
          ...
          VALUE_n;

Condition is a boolean expression
Mandatory else path, unless unconditional assignment
- Conditions may overlap
- Priority
Equivalent of “if …, elsif …, else” constructs

VHDL’87: The keyword ’else’ is also strictly necessary after each condition.

Notes

The signal assignment can be extended by the specification of conditions.

The condition is appended after the new value and is introduced by the keyword ’when’.

VHDL'87: The keyword ’else’ is also strictly necessary after each condition. (as an unconditional signal assignment has to be present.)

Consequently, using VHDL'87 standard it is not possible to generate storage elements with an conditional signal assignment. Otherwise the behavior is equivalent to the if …, elsif …, else … construct that is used within processes.

-- VHDL’93
Q <= '0' when RESET='1' else
      D  when ENABLE='1';

“when” condition after last “else” present ➔ a LATCH gets inferred, yuck!

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

6.2.1.2 Level-sensitive storage from concurrent signal assignment

“A level-sensitive storage element (=Latch) shall be modeled for a signal that is assigned in a concurrent signal assignment statement that can be mapped to a process that adheres to the rules in 6.2.1.1.”

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

6.2.1.1 Level-sensitive storage from process with sensitivity list

“A level-sensitive storage element (=Latch) shall be modeled for a signal (or variable) when all the following apply:

The signal (or variable) has an explicit assignment.
The signal (or variable) does not have an execution path with <clock_edge> as a condition.
There are executions that do not execute an explicit assignment to the signal (or variable).”

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

6.4 Combinational logic

“Any process that does not contain a clock edge or wait statement shall model either combinational logic or level-sensitive sequential logic. If there is always an assignment to a variable or signal in all possible executions of the process and all variables and signals have well-defined values, then the variable or signal models combinational logic.”

➔ so if not, a Latch could be generated…

Notes

If the variable or signal is updated before it is read in all executions of a process, then it shall model combinational logic.
If a variable or signal is read before it is updated, then it may model combinational logic.

entity CONDITIONAL_ASSIGNMENT is
  port (A, B, C, X : in  bit_vector (3 downto 0);
        Z_CONC     : out bit_vector (3 downto 0);
        Z_SEQ      : out bit_vector (3 downto 0));
end CONDITIONAL_ASSIGNMENT;
 
architecture EXAMPLE of CONDITIONAL_ASSIGNMENT is
begin
  -- Concurrent version of conditional signal assignment
  Z_CONC <= B when X = "1111" else
            C when X > "1000" else
            A;
 
  -- Equivalent sequential statements:
  process (A, B, C, X)
  begin
    if (X = "1111") then
      Z_SEQ <= B;
    elsif (X > "1000") then
      Z_SEQ <= C;
    else
      Z_SEQ <= A;
    end if;
  end process;
end EXAMPLE;

Notes

In the example, two equivalent descriptions of a simple multiplexer are given.

Please note that all signals appearing on the right side of the signal assignment operator are entered into the process’ sensitivity list.

The unconditional else path could be replaced by an unconditional (default) signal assignment in front of the if statement.

This “default” assignments would be overwritten, if any of the conditions were true.

with EXPRESSION select
 
  TARGET <= VALUE_1 when CHOICE_1,
            VALUE_2 when CHOICE_2 | CHOICE_3,
            VALUE_3 when CHOICE_4 to CHOICE_5,
            ...
            VALUE_n when others;

Choice options must not overlap
All choice options have to be covered
- Single values
- Value ranges
- Selection of values (“I” means “or”)
- “when others” covers all remaining choice options ➔ is mandatory!
Equivalent of “case …, when …” constructs

Notes

The behavior of the so called selected signal assignment is similar to the case statement.

It suffers from the same restrictions as its sequential counterpart, namely that all possible choice options have to be covered and none of the choice options may overlap with another.

entity SELECTED_ASSIGNMENT is
  port (A, B, C, X : in  integer range 0 to 15;
        Z_CONC     : out integer range 0 to 15;
        Z_SEQ      : out integer range 0 to 15);
end SELECTED_ASSIGNMENT;
 
architecture EXAMPLE of SELECTED_ASSIGNMENT is
begin
  -- Concurrent version of selected signal assignment
  with X select
    Z_CONC <= A when 0,
              B when 7 | 9,
              C when 1 to 5,
              0 when others;
  -- Equivalent sequential statements:
  process (A, B, C, X)
  begin
    case X is
      when 0      => Z_SEQ <= A;
      when 7 | 9  => Z_SEQ <= B;
      when 1 to 5 => Z_SEQ <= C;
      when others => Z_SEQ <= 0;
    end case;
  end process;
end EXAMPLE;

Notes

Like with conditional signal assignments, the signal assignment operator ’⇐’ can be seen as the core of the construct.

Again, the choice options are appended after the keyword ’when’, yet the different assignment alternatives are separated by ’,’ symbols. The equivalent of the ’case EXPRESSION is’ construct from the case statement must be placed as header line in front of the actual assignment specification. The keywords have to be translated, however, to ’with EXPRESSION select’.

Summary

Modeling of multiplexers
- Conditional signal assignment: decision based upon several signals
- Selected signal assignment: decision based upon values of an expression

“Shortcuts” for sequential statements:
- Conditional signal assignment ⇔ if …, elsif …, else …, end if
- Selected signal assignment ⇔ case …, when …, end case

Unconditional else path is mandatory in conditional signal assignment, otherwise: ➔ unwanted Latch inferred

Notes

All concurrent statements describe the functionality of multiplexer structures.

VHDL'87: It is impossible to model storage elements, like flip flops with concurrent statements, only.

Consequently, the unconditional else path is necessary in conditional signal assignments.

Every concurrent signal assignment, whether conditional or selected, can be modelled with a process construct, however.

As sequentially executed code is easier comprehensible, the concurrent versions should be used as shortcut when simple functionality would be obfuscated by the process overhead, only.

Concurrent statements ...

...are only executed, when a signal changes, that is read in the statement.
...appear in the statement part of an architecture.

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Chapters of System Design > VHDL Language and Syntax

Concurrent Statements

Introduction

Notes

Conditional Signal Assignment (CSA)

Notes

VHDL’93: Conditional Signal Assignment

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

VHDL RTL-Synthesis Standard (IEEE 1076.6:2004)

Notes

Conditional Signal Assignment: Example

Notes

Selected Signal Assignment (SSA)

Notes

Selected Signal Assignment: Example

Notes

Summary

Notes

Quiz

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