Subprogram Declaration and Overloading
Introduction
- Subprograms may be declared/defined in any declaration part
- Package
- Entity
- Architecture
- Process
- Subprogram
- Overloading of subprograms possible
- Identical name
- Different parameters
- Works with any kind of subprogram
- During compilation/runtime that subprogram is called whose formal parameter match the provided actuals
Notes
Subprograms may be declared/defined in any declarative part of a VHDL object. The actual definition of the behavior may also be separated from the declaration, which is often the case when packages are split into package and package body. The usual object visibility rules apply, e.g. a subprogram which is declared in a package may be used in all units that reference this package. Subprograms that are declared within another subprogram are available within this “parent” subprogram, only.
It is legal to declare subprograms with identical names, as long as they are distinguishable by the compiler. Thus, if the two subprogram names match, the parameter set/return values have to differ. This is called overloading and is allowed for all subprograms. It is especially useful when applied to operators, which can be seen as functions with a special name. This allows, for example, to use the conventional ’+’ symbol for the addition of integer values and, likewise, with bit vectors that should be interpreted as numbers.
During compilation that procedure is chosen whose formal parameters match the actual parameters in the procedure call.
Overloading Example
procedure READ(L : inout line; VALUE : out character; GOOD : out boolean); procedure READ(L : inout line; VALUE : out character); procedure READ(L : inout line; VALUE : out integer; GOOD : out boolean ); procedure READ(L : inout line; VALUE : out integer ); ...
- Input routines from TEXTIO package
- Extract different data types from a line
- Identical names
- Different numbers of parameters
- Different parameter types
Notes
The file I/O procedures read, write, readline, writeline and the line types are predefined in the standard TEXTIO package. Several overloaded read/write procedures for the standard data types are declared. They extract a value of the desired type from a file line. The line itself is modified, as indicated by the mode declaration ’inout’, i.e. several values may be read from a single line.
It is not possible to declare two subprograms which have the same number of parameters and the same types but different names, modes or classes. The compiler will report an error message similar to “illegal redeclaration”.
Overloading - Illegal Redeclarations
package P_EXAMPLE is -- 1 -- procedure TEST(A : bit; variable X_VAR : out integer); -- 2 -- procedure TEST(B : bit; variable X_VAR : out integer); -- 3 -- procedure TEST(A : bit; variable X_VAR : in integer); -- 4 -- procedure TEST(A : bit; signal X_SIG : out integer); -- 5 -- procedure TEST(A : bit; signal X_SIG : out integer; FOO : boolean := false); end P_EXAMPLE;
- Relevant information for overloading:
- Number of formal parameters
- Types of the formal parameters
- Order of the parameter types
- VHDL compiler ignore the following differences in parameter declarations:
- Names of formal parameters (2)
- Mode/class of formal parameter (3/4)
- Default values may be assigned to input parameters
The example package P_EXAMPLE will not compile successfully unless the declarations (2)-(4) are removed, e.g. by marking them as comments.
Notes
These four procedures have the same name as the first one and all of them need a bit and an integer parameter. If a subprogram is necessary to deal with signal and variable parameters, it is possible to declare an additional dummy input parameter and assign it a default value. This way, the declared subprograms differ in the number of parameter and a redeclaration error is avoided.
Overloading - Ambiguity
-- Declarations 2-4 need to be removed from the -- package P_EXAMPLE in order to compile! use work.P_EXAMPLE.all; entity AMBIGUITY is end AMBIGUITY; architecture EXAMPLE of AMBIGUITY is signal A: bit; signal X_SIG: integer; begin process variable X_VAR: integer; begin -- 1 -- TEST(A, X_VAR); -- 2 -- TEST(A, X_SIG); -- 3 -- TEST(A => A, X_SIG => X_SIG); -- 4 -- TEST(A => A, X_VAR => X_VAR); wait; end process; end EXAMPLE;
new package P_EXAMPLE only holds:
-- 1 -- procedure TEST(A : bit; variable X_VAR : out integer); -- 5 -- procedure TEST(A : bit; signal X_SIG : out integer FOO : boolean := false);
- Ambiguous calls occur, if it is not possible to find a unique subprogram by
- name
- number of formal parameters
- types and order of actual parameters (1/2)
- name of formal parameters (named association, only)
Notes
Additionally, it is necessary to use the named association mechanism to map the actual parameters to the formal ones that were declared. Otherwise, the compiler will try to find an unique subprogram of the given name which has the same number and type of parameters as in the call. If this fails, an error message about an ambiguous expression will be generated (TEST statements 1, 2).
Input parameters with a default value assigned to them need not be present in the subprogram call. Their use is not recommended, however, as some synthesis tools map absent parameters to the default value of the data type (type’left) which may lead to a different behavior, if the parameter is actually used in the body.
Operator Overloading
- Similar to function declarations
- Name = existing operator symbol, enclosed in quotation marks
- Operand left/right of operator are mapped to first/second parameter
- Extends operator functionality to new data types
- Operator call according to the individual context
- Definition of new operators is not allowed
Notes
All standard VHDL operators can be overloaded but is not allowed to define new operators. Operator declarations are equivalent to function declarations apart from the name which must be placed in quotation marks (“). The number of parameters is also fixed and can not be modified. In case of binary operators, i.e. operators with two operands, the left/right operand are mapped to the leftmost/rightmost parameter, respectively.
Operator Overloading - Example
package P_BIT_ARITH is function "+" (L: bit_vector; R: bit_vector) return bit_vector; --1 function "+" (L: integer; R: bit_vector) return bit_vector; --2 function "+" (L: bit_vector; R: integer) return bit_vector; --3 function "+" (L: bit_vector; R: bit_vector) return integer; --4 end P_BIT_ARITH; use work.P_BIT_ARITH.all; entity OVERLOADED is port(A_VEC, B_VEC : in bit_vector(3 downto 0); A_INT, B_INT : in integer range 0 to 15; Q_VEC : out bit_vector(3 downto 0); Q_INT : out integer range 0 to 15); end OVERLOADED; architecture EXAMPLE of OVERLOADED is begin Q_VEC <= A_VEC + B_VEC; -- a Q_VEC <= A_INT + B_VEC; -- b Q_VEC <= A_VEC + B_INT; -- c Q_VEC <= A_INT + B_INT; -- d Q_INT <= A_VEC + B_VEC; -- e Q_INT <= A_INT + B_INT; -- f end EXAMPLE;
Notes
The code example shows just the operator declarations and their use. The behavior has to be defined in a package body, if the design is to be simulated. During compilation, the VHDL compiler searches its list of operator declarations for a parameter list with matching data types.
This way, the function bodies of the operator declarations (1)-(3) will be used in the signal assignments (a)-©. Signal assignment (d) will result in an error message as the addition of two integer values to obtain a bit_vector has not been defined, yet.
Assignment (e) matches the parameter list of declaration (4) and the last assignment will use the standard VHDL operator. Arithmetic operations based on the data type ’bit’ are defined in the standard package ’numeric_bit’ (library IEEE). In practice, this data type should be avoided, however, as standard packages are available that define more powerful bit vector types and the corresponding operations.
Quiz
Chapters of System Design > VHDL Language and Syntax