courses:system_design:vhdl_language_and_syntax:extended_data_types:arrays

Arrays

type STD_ULOGIC_VECTOR is
  array (natural range <>) of STD_ULOGIC;
type MY_BYTE is array(7 downto 0) of STD_ULOGIC;
signal BYTE_BUS : STD_ULOGIC_VECTOR (7 downto 0);
signal TYPE_BUS : MY_BYTE;
  • Definition of an array type
    • Constrained or unconstrained size
  • Declaration of a signal of that type
    • Range specification necessary
  • The index set can be of any type
architecture EXAMPLE of ARRAY is
  type CLOCK_DIGITS is
    (HOUR10,HOUR1,MINUTES10,MINUTES1);
  type T_TIME is array(CLOCK_DIGITS)
            of integer range 0 to 9;
  signal ALARM_TIME : T_TIME := (0,7,3,0);
 
begin
  ALARM_TIME(HOUR1)               <= 0;
  ALARM_TIME(HOUR10 to MINUTES10) <= (0,7,0);
end EXAMPLE;
Only integer index sets are supported by all synthesis tools

Notes

Arrays are a collection of a number of values of a single data type and are represented as a new data type in VHDL.

It is possible to leave the range of array indices open at the time of definition. These so called unconstrained arrays can not be used as signals, however, i.e. the index range has to be specified in the signal declaration then. The advantage of unconstrained arrays is the possibility to concatenate objects of different lengths, for example, because they are still of the same data type.

This would not be allowed if each array length was declared as separate data type. VHDL does not put any restrictions on the index set of arrays, as long it is a discrete range of values. It is even legal to use enumeration types, as shown in the code example, although this version is not generally synthesizable.

architecture EXAMPLE of ARRAY is
 
 type INTEGER_VECTOR is
      array (1 to 8) of integer;
 
  -- 1 --
  type MATRIX_A is array(1 to 3) of
      INTEGER_VECTOR;
 
  -- 2 --
  type MATRIX_B is array(1 to 4, 1 to 8)
      of integer;
 
 signal MATRIX3x8 : MATRIX_A;
 signal MATRIX4x8 : MATRIX_B;
 
begin
 
 MATRIX3x8(3)(5)  <= 10;  -- array of array
 
 MATRIX4x8(4, 5)  <= 17;  -- 2 dim array
 
end EXAMPLE;
  • Two possibilities
    • Array of array
    • Multidimensional array
  • Different referencing
  • Barely supported by synthesis tools

Notes

Multidimensional arrays can simply be obtained by defining a new data type as array of another array data type (1). When accessing its array elements, the selections are processed from left to right, i.e. the leftmost pair of brackets selects the index range for the “outermost” array. Thus ’MATRIX_3x8(2)’ selects the second ’INTEGER_VECTOR’ of ’MATRIX_A’.

The range enclosed in the next pair applies to the array that is returned by the previous slice selection, i.e. ’MATRIX_3x8(2)(4)’ returns the fourth integer value of this ’INTEGER_VECTOR’. Multiple dimensions can also be specified directly within a new array definition (2). The ranges of the different dimensions are separated by ’,’ symbols. If a whole row or column is to be selected, the range has to be provided in the slice selection. Multidimensional arrays are generally synthesizable up to dimension 2, only.

architecture EXAMPLE of AGGREGATE is
  type INTEGER_VECTOR is
      array (1 to 8) of integer;
  type MATRIX_A is
      array(1 to 3) of INTEGER_VECTOR;
   type MATRIX_B is
      array(1 to 4, 1 to 8) of integer;
 
  signal MATRIX3x8 : MATRIX_A;
  signal MATRIX4x8 : MATRIX_B;
  signal VEC0, VEC1 : INTEGER_VECTOR;
  signal VEC2, VEC3 : INTEGER_VECTOR;
begin
 
  MATRIX3x8 <= (VEC0, VEC1, VEC2);
  MATRIX4x8 <= (VEC0, VEC1, VEC2, VEC3);
 
  MATRIX3x8 <= (others => VEC3);
  MATRIX4x8 <= (others => VEC3);
 
  MATRIX3x8 <= (others => (others => 5));
  MATRIX4x8 <= (others => (others => 5));
end EXAMPLE;
  • Aggregates may be nested
  • Aggregates can be used to make assignments to all elements of a multidimensional array

Notes

The most convenient way to assign values to multiple array elements is via the aggregate mechanism. Aggregates can also be nested for this purpose. With an aggregate one can assign to all elements of an array a specific value in a clear fashion.


Chapters of System Design > VHDL Language and Syntax > Extended Data Types