COMPARATORS library
The COMPARATORS library consists of the following 3 generic components:
- eqN: N-bit equality comparator
- gleNs: N-bit greater-less-equal signed number magnitude comparator
- gleNu: N-bit greater-less-equal unsigned number magnitude comparator
The COMPARATORs library can be verified with this testbench: test_comparators
eqN
- comparators.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : comparators.vhd # -- # # -- # Component : eqN : N-Bit Equality comparator # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.ALL; -- eqN Entity Description entity eqN is generic(N: INTEGER := 4); port( A: in unsigned(N-1 downto 0); B: in unsigned(N-1 downto 0); EQ: out std_ulogic ); end eqN; -- eqN Architecture Description architecture rtl of eqN is begin -- A = B eq <= '1' WHEN (A = B) ELSE '0'; end rtl;
gleNs
- comparators.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : comparators.vhd # -- # # -- # Component : gleNs : N-Bit greate-less-equal signed magnitude comp. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.ALL; -- gleNs Entity Description entity gleNs is generic(N: INTEGER := 4); port( A: in signed(N-1 downto 0); B: in signed(N-1 downto 0); EQ,GT,LT: buffer std_ulogic ); end gleNs; -- gleNs Architecture Description architecture rtl of gleNs is signal SignGreater,gt1,gt2 : std_ulogic; begin -- A = B eq <= '1' WHEN (A = B) ELSE '0'; -- A > B SignGreater <= '1' WHEN (B(N-1) > A(N-1)) ELSE '0'; gt1 <= '1' WHEN (A>B) ELSE '0'; gt2 <= NOT A(N-1) OR B(N-1); gt <= (gt1 AND gt2) OR SignGreater; -- A < B lt <= (NOT eq) AND (NOT gt); end rtl;
gleNu
- comparators.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : comparators.vhd # -- # # -- # Component : gleNu : N-Bit greate-less-equal unsigned comparator # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.ALL; -- gleNu Entity Description entity gleNu is generic(N: INTEGER := 4); port( A: in unsigned(N-1 downto 0); B: in unsigned(N-1 downto 0); EQ,GT,LT: out std_ulogic ); end gleNu; -- gleNu Architecture Description architecture rtl of gleNu is begin -- A = B eq <= '1' WHEN (A = B) ELSE '0'; -- A > B gt <= '1' WHEN (A > B) ELSE '0'; -- A < B lt <= '1' WHEN (A < B) ELSE '0'; end rtl;
Testbench
- test_comparators.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_comparators.vhd # -- # # -- # Component : test_comparators : Test Bench for various comparatos. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity test_comparators IS END test_comparators; ARCHITECTURE rtl OF test_comparators IS COMPONENT eqN is generic(N: INTEGER := 4); port( A: in unsigned(N-1 downto 0); B: in unsigned(N-1 downto 0); EQ: out std_ulogic ); end COMPONENT; COMPONENT gleNs is generic(N: INTEGER := 4); port( A: in signed(N-1 downto 0); B: in signed(N-1 downto 0); EQ,GT,LT: buffer std_ulogic ); end COMPONENT; COMPONENT gleNu is generic(N: INTEGER := 4); port( A: in unsigned(N-1 downto 0); B: in unsigned(N-1 downto 0); EQ,GT,LT: out std_ulogic ); END COMPONENT; FOR ALL : eqN USE ENTITY WORK.eqN(rtl); FOR ALL : gleNs USE ENTITY WORK.gleNs(rtl); FOR ALL : gleNu USE ENTITY WORK.gleNu(rtl); CONSTANT N : integer := 8; SIGNAL A_u,B_u : unsigned(N-1 downto 0); SIGNAL A_s,B_s : signed(N-1 downto 0); SIGNAL EQ0,EQ1,GT1,LT1,EQ2,GT2,LT2 : std_ulogic; BEGIN Equality : eqN GENERIC MAP ( N=>N ) PORT MAP ( A=>A_u, B=>B_u, EQ=>EQ0 ); Comparator_unsigned : gleNu GENERIC MAP ( N=>N ) PORT MAP ( A=>A_u, B=>B_u, EQ=>EQ1, GT=>GT1, LT=>LT1 ); Comparator_signed : gleNs GENERIC MAP ( N=>N ) PORT MAP ( A=>A_s, B=>B_s, EQ=>EQ2, GT=>GT2, LT=>LT2 ); A_u <= "10101000", "01011001" AFTER 100 ns, "11011011" AFTER 200 ns, "01101001" AFTER 300 ns; B_u <= "00111000", "01001011" AFTER 100 ns, "01010001" AFTER 200 ns, "11001001" AFTER 300 ns; A_s <= "10101000", "01011001" AFTER 100 ns, "11011011" AFTER 200 ns, "01101001" AFTER 300 ns; B_s <= "00111000", "01001011" AFTER 100 ns, "01010001" AFTER 200 ns, "11001001" AFTER 300 ns; END rtl;