-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    comparators.vhd                                          #
-- #                                                                          #
-- # Component  :    eqN : N-Bit Equality comparator                          #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;

-- eqN Entity Description
entity eqN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      B: in unsigned(N-1 downto 0);
      EQ: out std_ulogic
   );
end eqN;

-- eqN Architecture Description
architecture rtl of eqN is
begin
   -- A = B
   eq <= '1' WHEN (A = B) ELSE '0';
    
end rtl;