-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : comparators.vhd # -- # # -- # Component : gleNu : N-Bit greate-less-equal unsigned comparator # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.ALL; -- gleNu Entity Description entity gleNu is generic(N: INTEGER := 4); port( A: in unsigned(N-1 downto 0); B: in unsigned(N-1 downto 0); EQ,GT,LT: out std_ulogic ); end gleNu; -- gleNu Architecture Description architecture rtl of gleNu is begin -- A = B eq <= '1' WHEN (A = B) ELSE '0'; -- A > B gt <= '1' WHEN (A > B) ELSE '0'; -- A < B lt <= '1' WHEN (A < B) ELSE '0'; end rtl;