-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : comparators.vhd # -- # # -- # Component : gleNs : N-Bit greate-less-equal signed magnitude comp. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.ALL; -- gleNs Entity Description entity gleNs is generic(N: INTEGER := 4); port( A: in signed(N-1 downto 0); B: in signed(N-1 downto 0); EQ,GT,LT: buffer std_ulogic ); end gleNs; -- gleNs Architecture Description architecture rtl of gleNs is signal SignGreater,gt1,gt2 : std_ulogic; begin -- A = B eq <= '1' WHEN (A = B) ELSE '0'; -- A > B SignGreater <= '1' WHEN (B(N-1) > A(N-1)) ELSE '0'; gt1 <= '1' WHEN (A>B) ELSE '0'; gt2 <= NOT A(N-1) OR B(N-1); gt <= (gt1 AND gt2) OR SignGreater; -- A < B lt <= (NOT eq) AND (NOT gt); end rtl;