LAB 8: A Timer

After a picture has been taken, the film is transported forward automatically. In order to detect malfunction, e.g. end of film or a torn film, a transport supervision module needs to be implemented. If the servo motor has not finished the film transport after 2 seconds, an error signal is generated.

The timeout function is generated with the help of a counter. As the clock frequency is 8192 Hz, 2 seconds correspond to a maximum value of 16383 (=14 bit). The CLK and RESET signals are needed for the Flip-Flops again.

The start of the film transport is signaled via the MOTOR_GO signal. It is set to ’1’ when the transportation begins. When the servo motor has finished, the MOTOR_READY signal is set to ’1’. An error is reported via the MOTOR_ERROR signal in the same way, i.e. it is set to ’1’ if the MOTOR_READY pulse has not occurred in time. The signals are active for the duration of one clock period, only, in order to make an edge detection dispensable.

The interface of the module is depicted in the next drawing:

TODO Bild The transport timeout supervision module

Usually, the reset strategy is defined for the complete design. As an asynchronous reset was used in the first clocked module, we have to use the same template for clocked processes as before.

The timeout counter is started whenever a ’1’ is detected on the MOTOR_GO signal. The counter is stopped either if the MOTOR_READY signal is set to ’1’ or if the counter reaches its maximum value. In the last case, the MOTOR_ERROR is set to ’1’ for one clock cycle.

The module processes and generates control signals, only. They are of type std_ulogic, as usual. The counter is most easily implemented by a counter variable of type integer.

• Create a new VHDL file for the MOTOR_TIMER module.
• Write a testbench to verify the design. The clock period is approx. 122.07 us, in case you want to use realistic time values for the stimuli generation.
• Compile and simulate the design.
• How many Flip Flops are generated? Synthesize the design and compare your answer with the synthesis result.

MOTOR_TIMER.VHD

library ieee;
use ieee.std_logic_1164.all;
 
entity MOTOR_TIMER is
  port(CLK         : in std_ulogic;
       RESET       : in std_ulogic;
       MOTOR_GO    : in std_ulogic;
       MOTOR_READY : in std_ulogic;
       MOTOR_ERROR : out std_ulogic);
end MOTOR_TIMER;
 
architecture RTL of MOTOR_TIMER is
begin
  -- Clocked process with asynchronous reset
  process
    -- Variables for timeout counter value and counter active flag
  begin
    if (RESET = '1') then
      -- Reset values for all registers
    elsif (CLK'event and CLK = '1') then
      if MOTOR_GO = '1' then
        -- Start timeout detector
      end if;
 
      if MOTOR_READY = '1' then
        -- Stop timeout detector
      end if;
 
      if COUNT = '1' then
        -- Counter with overflow detection
      end if; -- if COUNTING
    end if; -- end of clocked process
  end process;
end RTL;

TB_MOTOR_TIMER.VHD

library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
 
entity TB_MOTOR_TIMER is
end TB_MOTOR_TIMER;
 
architecture TEST of TB_MOTOR_TIMER is
  constant PERIOD : time := 1 sec/8192;
 
  component MOTOR_TIMER
    port(CLK         : in std_ulogic;
         RESET       : in std_ulogic;
         MOTOR_GO    : in std_ulogic;
         MOTOR_READY : in std_ulogic;
         MOTOR_ERROR : out std_ulogic);
  end component;
 
  signal W_CLK         : std_ulogic := '0';
  signal W_RESET       : std_ulogic;
  signal W_MOTOR_GO    : std_ulogic;
  signal W_MOTOR_READY : std_ulogic;
  signal W_MOTOR_ERROR : std_ulogic;
 
begin
  DUT : MOTOR_TIMER
    port map(
      CLK         => W_CLK,
      RESET       => W_RESET,
      MOTOR_GO    => W_MOTOR_GO,
      MOTOR_READY => W_MOTOR_READY,
      MOTOR_ERROR => W_MOTOR_ERROR);
 
  W_CLK <= not W_CLK after PERIOD/2;
 
  STIMULI : process
  begin
    W_RESET       <= '1';
    W_MOTOR_GO    <= '1';
    W_MOTOR_READY <= '0';
    -- MOTOR_ERROR: '0'
    wait for 3*PERIOD;
 
    W_RESET    <= '0';
    W_MOTOR_GO <= '0';
    -- no changes
    wait for 2.1 sec;
 
    W_MOTOR_GO <= '1';
    wait for PERIOD;
    W_MOTOR_GO <= '0';
    -- MOTOR_ERROR -> '1' -> '0'
    wait for 2.1 sec;
 
    W_MOTOR_GO    <= '1';
    wait for PERIOD;
    W_MOTOR_GO    <= '0';
    wait for 1.9 sec;
    W_MOTOR_READY <= '1';
    wait for PERIOD;
    W_MOTOR_READY <= '0';
    -- MOTOR_ERROR remains '0';
    wait for 2.1 sec;
 
    assert false report "End of stimuli reached"
                 severity failure;
  end process STIMULI;
 
  SAMPLE : process(W_MOTOR_GO, W_MOTOR_ERROR)
    constant SPACE     : string := " ";
    variable FILE_LINE : line;
    FILE     OUT_FILE  : text IS OUT "lab_8.trace";
  begin
    write(FILE_LINE, now);
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_MOTOR_GO));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_MOTOR_ERROR));
 
    writeline(OUT_FILE, FILE_LINE);
  end process SAMPLE;
end TEST;
 
configuration CFG_TB_MOTOR_TIMER of TB_MOTOR_TIMER is
  for TEST
  end for;
end CFG_TB_MOTOR_TIMER;