LAB 10: A State Machine for the Main Controller

A main control unit is needed to coordinate the actions of the different modules. The interface of the module is depicted in the next drawing:

When the trigger button is pressed the shutter shall be opened and stay opened for the selected exposure time. This is done by setting the TIMER_GO signal one period to high, so the exposure controller opens the shutter for the selected exposure time. After the exposure time has passed the film has to be transported. So the motor needs a signal to start the transport Therefore MOTOR_GO is set to high for one period.

Now two things can appear: The motor has successfully transported the film, which is signalled by the MOTOR_READY signal. In this case a new photo can be made by the camera. It is the TRIGGER signal has to be examined again.

Or an error occurred while transporting the film. In this case the MOTOR_ERROR signal is set and the ERROR output signal has to be set, so the display indicate this case. When the cause of the error is removed (e.g. a new film is inserted) this has to be signalled by the user by pressing RESET or the trigger button once, but without taking a picture at the same time.

The current architecture will contain only one finite state machine. For that a combinational process, a clocked process and the concurrent output assignments are needed. In the clocked process the next state will be stored as the current state with every rising clock edge. Here the FlipFlops of the state machine are generated.

In the combinational process the next state will be evaluated in a case statement depending of the current state and the input values of TRIGGER, EXPOSE, MOTOR_READY and MOTOR_ERROR.

The output values are evaluated and assigned to the outputs in concurrent signal assignments. The expression in this assignment depend only on the current state. So a Moore machine has to be implemented!

The main controller deals purely with control signals, i.e. only std_ulogic is used for the entity ports. Additionally, an internal signal is necessary to store the current controller state. You should define your own enumeration type for this purpose which holds all possible states of the finite state machine.

• Create the new VHDL file.
• Write a testbench to verify the design. Use assertions to check the exposure times during the simulation run.
• Compile and simulate the design.
• Compare the number of Flip Flops that you would expect with the synthesis result.

MAIN_CTRL.VHD

library ieee;
use ieee.std_logic_1164.all;
 
entity MAIN_CTRL is
  -- system signals: CLK, RESET
  -- control signals: TRIGGER, EXPOSE, MOTOR_READY, MOTOR_ERROR
  -- output signals: ERROR, TIMER_GO, MOTOR_GO
end MAIN_CTRL;
 
architecture RTL of MAIN_CTRL is
  -- The state machine has to control the exposure process:
  -- While in IDLE state, the device waits for a trigger signal
  -- Then the exposure controller is started and the main controller
  -- has to wait for the end of the exposure. Please note, that the
  -- exposure controller needs 1 clock cycle to react on input signal
  -- changes!
  -- After the picture has been taken, the film transport must be
  -- initiated and the camera has to wait for the motor to finish
  -- If an error occurs, the controller shall enter a BROKEN state
  -- to prevent any further damage to the film
 
  -- Signals to store the state information:
  signal STATE      : T_STATE;
  signal NEXT_STATE : T_STATE;
 
begin
  -- process to calculate the next state
  begin
    -- Keep the old state as default action
    -- Check all transitions
    case STATE is
      when IDLE =>
      when TAKE_PIC =>
      when DELAY =>
      when WAIT_EXP_TIME =>
      -- Other states
      when others =>
        NULL;
    end case;
  end process;
 
  -- Clocked process to update the FSM registers
  begin
    if (RESET = '1') then
      -- Default system state
    elsif (CLK'event and CLK = '1') then
      -- Update of register values
    end if; -- end of clocked process
  end process;
 
  -- Concurrent statements to drive the output signals with STATE select
  ERROR <= '1' when BROKEN,
           '0' when others;
end RTL;

TB_MAIN_CTRL.VHD

library ieee;
use std.textio.all;
use ieee.std_logic_1164.all;
 
entity TB_MAIN_CTRL is
end TB_MAIN_CTRL;
 
architecture TEST of TB_MAIN_CTRL is
  constant PERIOD : time := 10 ns;
 
  component MAIN_CTRL
    port(CLK         : in std_ulogic;
         RESET       : in std_ulogic;
         TRIGGER     : in std_ulogic;
         EXPOSE      : in std_ulogic;
         MOTOR_READY : in std_ulogic;
         MOTOR_ERROR : in std_ulogic;
         ERROR       : out std_ulogic;
         TIMER_GO    : out std_ulogic;
         MOTOR_GO    : out std_ulogic);
  end component;
 
  signal W_CLK         : std_ulogic := '0';
  signal W_RESET       : std_ulogic;
  signal W_TRIGGER     : std_ulogic;
  signal W_EXPOSE      : std_ulogic;
  signal W_MOTOR_READY : std_ulogic;
  signal W_MOTOR_ERROR : std_ulogic;
  signal W_ERROR : std_ulogic;
  signal W_TIMER_GO : std_ulogic;
  signal W_MOTOR_GO : std_ulogic;
 
begin
  DUT : MAIN_CTRL
    port map(
      CLK         => W_CLK,
      RESET       => W_RESET,
      TRIGGER     => W_TRIGGER,
      EXPOSE      => W_EXPOSE,
      MOTOR_READY => W_MOTOR_READY,
      MOTOR_ERROR => W_MOTOR_ERROR,
      ERROR       => W_ERROR,
      TIMER_GO    => W_TIMER_GO,
      MOTOR_GO    => W_MOTOR_GO);
 
  W_CLK <= not W_CLK after PERIOD/2;
 
  STIMULI : process
  begin
    W_RESET       <= '1';
    W_TRIGGER     <= '1';
    W_MOTOR_READY <= '0';
    W_MOTOR_ERROR <= '1';
    wait for 3*PERIOD;
 
    W_RESET       <= '0';
    W_TRIGGER     <= '0';
    W_MOTOR_READY <= '0';
    W_MOTOR_ERROR <= '0';
    wait for 10*PERIOD;
 
    W_TRIGGER <= '1';
    wait for PERIOD;
    W_TRIGGER <= '0';
    wait for 20*PERIOD;
 
    W_TRIGGER <= '1';
    wait for PERIOD;
    W_TRIGGER <= '0';
    wait for 5*PERIOD;
 
    W_MOTOR_READY <= '1';
    wait for PERIOD;
    W_MOTOR_READY <= '0';
    wait for 5*PERIOD;
 
    W_TRIGGER <= '1';
    wait for 15*PERIOD;
 
    W_MOTOR_READY <= '1';
    wait for PERIOD;
    W_MOTOR_READY <= '0';
    wait for 15*PERIOD;
 
    W_MOTOR_READY <= '1';
    wait for PERIOD;
    W_MOTOR_READY <= '0';
    wait for 15*PERIOD;
 
    W_MOTOR_READY <= '1';
    wait for PERIOD;
    W_MOTOR_READY <= '0';
    wait for 15*PERIOD;
 
    W_MOTOR_ERROR <= '1';
    wait for PERIOD;
    W_MOTOR_ERROR <= '0';
    W_MOTOR_READY <= '1';
    wait for 15*PERIOD;
 
    assert false report "End of stimuli reached"
                 severity failure;
  end process STIMULI;
 
  SAMPLE : process(W_TRIGGER, W_EXPOSE, W_MOTOR_READY, W_MOTOR_ERROR,
                   W_ERROR, W_TIMER_GO, W_MOTOR_GO)
    constant SPACE     : string := " ";
    variable FILE_LINE : line;
    FILE     OUT_FILE  : text IS OUT "lab_10.trace";
  begin
    write(FILE_LINE, now);
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_TRIGGER));
    write(FILE_LINE, to_bit(W_EXPOSE));
    write(FILE_LINE, to_bit(W_MOTOR_READY));
    write(FILE_LINE, to_bit(W_MOTOR_ERROR));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_ERROR));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_TIMER_GO));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, to_bit(W_MOTOR_GO));
    writeline(OUT_FILE, FILE_LINE);
  end process SAMPLE;
 
  TIMER : process
  begin
    W_EXPOSE <= '0';
    wait until W_TIMER_GO'EVENT and W_TIMER_GO = '1' and W_RESET = '0';
 
    wait for PERIOD;
    W_EXPOSE <= '1';
    wait for 10*PERIOD;
    W_EXPOSE <= '0';
  end process TIMER;
end TEST;
 
configuration CFG_TB_MAIN_CTRL of TB_MAIN_CTRL is
  for TEST
  end for;
end CFG_TB_MAIN_CTRL;