library ieee; use ieee.std_logic_1164.all; entity MOTOR_TIMER is port(CLK : in std_ulogic; RESET : in std_ulogic; MOTOR_GO : in std_ulogic; MOTOR_READY : in std_ulogic; MOTOR_ERROR : out std_ulogic); end MOTOR_TIMER; architecture RTL of MOTOR_TIMER is begin -- Clocked process with asynchronous reset process -- Variables for timeout counter value and counter active flag begin if (RESET = '1') then -- Reset values for all registers elsif (CLK'event and CLK = '1') then if MOTOR_GO = '1' then -- Start timeout detector end if; if MOTOR_READY = '1' then -- Stop timeout detector end if; if COUNT = '1' then -- Counter with overflow detection end if; -- if COUNTING end if; -- end of clocked process end process; end RTL;