LAB 6: A Register

When an exposure time is selected by the user it has to be stored. Edge-triggered Flip-Flops are used for this purpose. The contents of the register are updated only with the rising edge of the clock signal. This way, differences in the path delay become irrelevant as long as the maximum delay is shorter than the clock period.

In addition to the clock signal a second enabling condition is needed in this case. Valid exposure times shall be stored until another exposure time is selected. Only legal button combinations are mapped to display values other than (0,0,0) by the decoder, i.e. it is sufficient to exclude this value triple from being stored.

The reset input signal is necessary to be able to bring the chip into a defined state, e.g. after power-up.

The complete interface of the register is shown in the following figure:

TODO Bild The exposure time latch

The reset shall be implemented asynchronously, i.e. a process with sensitivity list is the only viable option in this case. The following template for clocked processes has to be used:

if RESET
...
elsif RISING_CLOCK_EDGE
...

After a rising clock edge has been detected it must be checked whether a key was pressed. If yes, the new exposure time is stored in the register.

The exposure latch is used to store the exposure time, i.e. T_DIGITS is the appropriate type for the data signals. CLK and RESET are single bit control signals and shall therefore be of type std_ulogic.

• Write a new file with the VHDL description of the exposure latch.
• Write a testbench to verify the design. The periodic clock signal generation should be placed in a separate stimuli process!
• Compile and simulate the design.
• Synthesize the module.

EXP_FF.VHD

library ieee;
use ieee.std_logic_1164.all;
 
entity EXP_FF is
  port(CLK      : in std_ulogic;
       RESET    : in std_ulogic;
       KEY      : in T_DIGITS;
       EXP_TIME : out T_DIGITS);
end EXP_FF;
 
architecture RTL of EXP_FF is
begin
  process(CLK)
  begin
    if (RESET = '1') then
      -- Assign a default value
    elsif (CLK'event and CLK = '1') then
      -- Check for new input values
    end if;
  end process;
end RTL;

TB_EXP_FF.VHD

library ieee;
USE std.textio.ALL;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;
 
entity TB_EXP_FF is
end TB_EXP_FF;
 
architecture TEST of TB_EXP_FF is
  component EXP_FF
    port(CLK      : in std_ulogic;
         RESET    : in std_ulogic;
         KEY      : in T_DIGITS;
         EXP_TIME : out T_DIGITS);
  end component;
 
  signal W_CLK      : std_ulogic := '0';
  signal W_RESET    : std_ulogic;
  signal W_KEY      : T_DIGITS;
  signal W_EXP_TIME : T_DIGITS;
 
begin
  DUT : EXP_FF
    port map(
      CLK      => W_CLK,
      RESET    => W_RESET,
      KEY      => W_KEY,
      EXP_TIME => W_EXP_TIME);
 
  W_CLK <= not W_CLK after 10 ns;
 
  STIMULI : process
  begin
    W_KEY <= (0,0,0);
    W_RESET <= '1';
    -- EXP_TIME = (0,0,1)
    wait for 5 ns;
 
    W_RESET <= '0';
    -- no changes (all 0 shall be ignored)
    wait for 15 ns;
 
    W_KEY <= (1,2,3);
    -- no changes (no active clock edge)
    wait for 5 ns;
 
    W_KEY <= (2,2,3);
    -- EXP_TIME = (2,2,3)
    wait for 15 ns;
 
    W_KEY <= (0,3,5);
    -- EXP_TIME = (0,3,5)
    wait for 5 ns;
 
    assert false report "End of stimuli reached"
                 severity failure;
  end process STIMULI;
 
  SAMPLE : process(W_EXP_TIME)
    constant SPACE     : string := " ";
    variable FILE_LINE : line;
    FILE     OUT_FILE  : text IS OUT "lab_6.trace";
  begin
    write(FILE_LINE, W_EXP_TIME(2));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, W_EXP_TIME(1));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, W_EXP_TIME(0));
 
    writeline(OUT_FILE, FILE_LINE);
  end process SAMPLE;
end TEST;
 
configuration CFG_TB_EXP_FF of TB_EXP_FF is
  for TEST
  end for;
end CFG_TB_EXP_FF;