library ieee;
USE std.textio.ALL;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;

entity TB_EXP_FF is
end TB_EXP_FF;

architecture TEST of TB_EXP_FF is
  component EXP_FF
    port(CLK      : in std_ulogic;
         RESET    : in std_ulogic;
         KEY      : in T_DIGITS;
         EXP_TIME : out T_DIGITS);
  end component;
  
  signal W_CLK      : std_ulogic := '0';
  signal W_RESET    : std_ulogic;
  signal W_KEY      : T_DIGITS;
  signal W_EXP_TIME : T_DIGITS;

begin
  DUT : EXP_FF
    port map(
      CLK      => W_CLK,
      RESET    => W_RESET,
      KEY      => W_KEY,
      EXP_TIME => W_EXP_TIME);

  W_CLK <= not W_CLK after 10 ns;
  
  STIMULI : process
  begin
    W_KEY <= (0,0,0);
    W_RESET <= '1';
    -- EXP_TIME = (0,0,1)
    wait for 5 ns;
    
    W_RESET <= '0';
    -- no changes (all 0 shall be ignored)
    wait for 15 ns;
    
    W_KEY <= (1,2,3);
    -- no changes (no active clock edge)
    wait for 5 ns;
    
    W_KEY <= (2,2,3);
    -- EXP_TIME = (2,2,3)
    wait for 15 ns;
    
    W_KEY <= (0,3,5);
    -- EXP_TIME = (0,3,5)
    wait for 5 ns;
    
    assert false report "End of stimuli reached"
                 severity failure;
  end process STIMULI;
  
  SAMPLE : process(W_EXP_TIME)
    constant SPACE     : string := " ";
    variable FILE_LINE : line;
    FILE     OUT_FILE  : text IS OUT "lab_6.trace";
  begin
    write(FILE_LINE, W_EXP_TIME(2));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, W_EXP_TIME(1));
    write(FILE_LINE, SPACE);
    write(FILE_LINE, W_EXP_TIME(0));
    
    writeline(OUT_FILE, FILE_LINE);
  end process SAMPLE;
end TEST;

configuration CFG_TB_EXP_FF of TB_EXP_FF is
  for TEST
  end for;
end CFG_TB_EXP_FF;