SHIFTERs library
The SHIFTERs library consists of the following 4 generic components:
- siso: N-bit serial-in / serial-out register
- piso: N-bit serial & parallel-in / serial-out register
- sispo: N-bit serial-in / serial & parallel-out register
- spispo: N-bit serial & parallel-in / serial & parallel-out register
The SHIFTERs library can be verified with this testbench: test_shifters
siso
- shifters.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : shifters.vhd # -- # # -- # Component : siso : Serial in - Serial Out shift register with # -- # direction control. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- siso Entity Description ENTITY siso IS GENERIC(x : INTEGER := 8); PORt( CLK,R,DIR_R,SE,SI: in std_ulogic; SO: out std_ulogic ); END siso; -- siso Architecture Description ARCHITECTURE rtl OF siso IS SIGNAL pre_Q : std_ulogic_vector((x-1) DOWNTO 0) := (OTHERS => 'X'); begin SHIFT_REGISTER_Process: process(CLK,R) BEGIN IF (R = '1') THEN pre_Q <= (OTHERS => '0'); ELSIF (CLK'event AND (CLK = '1') AND (CLK'last_value = '0')) THEN IF (SE = '1') AND (DIR_R = '1') THEN pre_Q(x-1) <= SI; pre_Q((x-2) DOWNTO 0) <= pre_Q((x-1) DOWNTO 1); ELSIF (SE = '1') AND (DIR_R = '0') THEN pre_Q((x-1) DOWNTO 1) <= pre_Q((x-2) DOWNTO 0); pre_Q(0) <= SI; END IF; END IF; END process SHIFT_REGISTER_Process; SO <= pre_Q(0) WHEN DIR_R = '1' ELSE pre_Q(x-1) WHEN DIR_R = '0' ELSE 'X'; END rtl;
piso
- shifters.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : shifters.vhd # -- # # -- # Component : piso : Parallel in - Serial Out shift register with # -- # direction control. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; --************************** -- piso Entity Description * --************************** ENTITY piso IS GENERIC(x : INTEGER := 8); PORt( DIN: IN std_ulogic_vector(x-1 DOWNTO 0); CLK,LD,R,DIR_R,SE: IN STD_ULOGIC; SO: OUT STD_ULOGIC ); END piso; -- piso Architecture Description ARCHITECTURE rtl of PISO IS SIGNAL pre_Q : std_ulogic_vector((x-1) DOWNTO 0) := (OTHERS => 'X'); BEGIN SHIFT_REGISTER_Process: PROCESS(CLK,R) BEGIN IF (R = '1') THEN pre_Q <= (OTHERS => '0'); ELSIF (CLK'event and (CLK = '1') AND (CLK'last_value = '0')) THEN IF (LD = '1') THEN pre_Q <= DIN; ELSIF (SE = '1') AND (DIR_R = '1') THEN pre_Q(x-1) <= '0'; pre_Q((x-2) DOWNTO 0) <= pre_Q((x-1) DOWNTO 1); ELSIF (SE = '1') AND (DIR_R = '0') THEN pre_Q((x-1) DOWNTO 1) <= pre_Q((x-2) DOWNTO 0); pre_Q(0) <= '0'; END IF; END IF; END PROCESS SHIFT_REGISTER_Process; SO <= pre_Q(0) WHEN DIR_R = '1' ELSE pre_Q(x-1) WHEN DIR_R = '0' ELSE 'X'; END rtl;
sispo
- shifters.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : shifters.vhd # -- # # -- # Component : sispo : Serial in - Serial/Parallel Out shift register # -- # with direction control. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- sispo Entity Description ENTITY sispo IS GENERIC(x : INTEGER := 8); port( DOUT: OUT std_ulogic_vector((x-1) DOWNTO 0); CLK,R,DIR_R,SE,SI: IN STD_ULOGIC; SO: OUT STD_ULOGIC ); END sispo; -- sispo Architecture Description ARCHITECTURE rtl OF sispo IS SIGNAL pre_Q : std_ulogic_vector((x-1) DOWNTO 0) := (OTHERS => 'X'); BEGIN SHIFT_REGISTER_Process: PROCESS(CLK,R) BEGIN IF (R = '1') THEN pre_Q <= (OTHERS => '0'); ELSIF (CLK'event AND (CLK = '1') AND (CLK'last_value = '0')) THEN IF (SE = '1') AND (DIR_R = '1') THEN pre_Q((x-1)) <= SI; pre_Q((x-2) DOWNTO 0) <= pre_Q((x-1) DOWNTO 1); ELSIF (SE = '1') AND (DIR_R = '0') THEN pre_Q((x-1) DOWNTO 1) <= pre_Q((x-2) DOWNTO 0); pre_Q(0) <= SI; END IF; END IF; END PROCESS SHIFT_REGISTER_Process; -- Assign outputs DOUT <= pre_Q; SO <= pre_Q(0) WHEN DIR_R = '1' ELSE pre_Q((x-1)) WHEN DIR_R = '0' ELSE 'X'; end rtl;
spispo
- shifters.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : shifters.vhd # -- # # -- # Component : spispo : Serial/Parallel In/Out shift register # -- # with direction control. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; -- spispo Entity Description ENTITY spispo IS GENERIC(x : INTEGER := 8); port( DIN: IN std_ulogic_vector((x-1) DOWNTO 0); DOUT: OUT std_ulogic_vector((x-1) DOWNTO 0); CLK,LD,R,DIR_R,SE,SI: IN STD_ULOGIC; SO: OUT STD_ULOGIC ); END spispo; -- spisp Architecture Description ARCHITECTURE rtl OF spispo IS SIGNAL pre_Q : std_ulogic_vector((x-1) DOWNTO 0) := (OTHERS => 'X'); BEGIN SHIFT_REGISTER_Process: PROCESS(CLK,R) BEGIN IF (R = '1') THEN pre_Q <= (OTHERS => '0'); ELSIF (CLK'event AND (CLK = '1') AND (CLK'last_value = '0')) THEN IF (LD = '1') THEN pre_Q <= DIN; ELSIF (SE = '1') AND (DIR_R = '1') THEN pre_Q((x-1)) <= SI; pre_Q((x-2) DOWNTO 0) <= pre_Q((x-1) DOWNTO 1); ELSIF (SE = '1') AND (DIR_R = '0') THEN pre_Q((x-1) DOWNTO 1) <= pre_Q((x-2) DOWNTO 0); pre_Q(0) <= SI; END IF; END IF; END PROCESS SHIFT_REGISTER_Process; -- Assign outputs DOUT <= pre_Q; SO <= pre_Q(0) WHEN DIR_R = '1' ELSE pre_Q((x-1)) WHEN DIR_R = '0' ELSE 'X'; END rtl;
Testbench
- test_shifters.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_shifters.vhd # -- # # -- # Component : test_shifters : Test Bench for various shifters. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; entity test_shifters IS END test_shifters; ARCHITECTURE rtl OF test_shifters IS COMPONENT pis GENERIC(x : INTEGER); PORT( DIN: in std_ulogic_vector (x-1 DOWNTO 0); LD,CLK,R,DIR_R,SE: in std_ulogic; SO: out std_ulogic ); END COMPONENT; COMPONENT sis GENERIC(x : INTEGER); PORT( CLK,R,DIR_R,SE,SI: in std_ulogic; SO: out std_ulogic ); END COMPONENT; COMPONENT sisp GENERIC(x : INTEGER); PORt( DOUT: OUT STD_ULOGIC_VECTOR ( x-1 DOWNTO 0); CLK,R,DIR_R,SE,SI: in std_ulogic; SO: out std_ulogic ); END COMPONENT; COMPONENT spisp GENERIC(x : INTEGER); PORt( DIN: in std_ulogic_vector (x-1 DOWNTO 0); DOUT: OUT STD_ULOGIC_VECTOR ( x-1 DOWNTO 0); LD,CLK,R,DIR_R,SE,SI: in std_ulogic; SO: out std_ulogic ); END COMPONENT; FOR siso : sis USE ENTITY WORK.siso(rtl); FOR piso : pis USE ENTITY WORK.piso(rtl); FOR sispo : sisp USE ENTITY WORK.sispo(rtl); FOR spispo : spisp USE ENTITY WORK.spispo(rtl); SIGNAL CLK : std_ulogic := '0'; SIGNAL R : std_ulogic; SIGNAL DIR_R : std_ulogic; SIGNAL LD : std_ulogic; SIGNAL SE : std_ulogic; SIGNAL SI : std_ulogic; SIGNAL SO1 : std_ulogic; SIGNAL SO2 : std_ulogic; SIGNAL SO3 : std_ulogic; SIGNAL SO4 : std_ulogic; SIGNAL DIN : std_ulogic_vector( 7 DOWNTO 0); SIGNAL DOUT1 : std_ulogic_vector( 7 DOWNTO 0); SIGNAL DOUT2 : std_ulogic_vector( 7 DOWNTO 0); BEGIN piso: pis GENERIC MAP (x => 8) PORT MAP ( DIN => DIN, CLK => CLK, R => R, DIR_R => DIR_R, SE => SE, LD => LD, SO => SO1 ); siso: sis GENERIC MAP (x => 8) PORT MAP ( CLK => CLK, R => R, DIR_R => DIR_R, SI => SI, SE => SE, SO => SO2 ); sispo: sisp GENERIC MAP (x => 8) PORT MAP ( DOUT => DOUT1, CLK => CLK, R => R, DIR_R => DIR_R, SI => SI, SE => SE, SO => SO3 ); spispo: spisp GENERIC MAP (x => 8) PORT MAP ( DIN => DIN, DOUT => DOUT2, CLK => CLK, R => R, DIR_R => DIR_R, SI => SI, SE => SE, LD => LD, SO => SO4 ); SI <= '1' AFTER 40 ns, '0' AFTER 60 ns, '1' AFTER 80 ns, '0' AFTER 100 ns, '1' AFTER 120 ns, '0' AFTER 140 ns, '1' AFTER 160 ns; DIN <= "01010101" AFTER 50 ns; LD <= '1' AFTER 60 ns, '0' AFTER 80 ns; SE <= '1' AFTER 180 ns, '0' AFTER 340 ns; R <= '1' AFTER 20 ns, '0' AFTER 40 ns; DIR_R <= '1' AFTER 180 ns, '0' AFTER 220 ns; CLK <= NOT CLK AFTER 10 ns; END rtl;