-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_shifters.vhd                                        #
-- #                                                                          #
-- # Component  :    test_shifters : Test Bench for various shifters.         #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test_shifters IS

END test_shifters;

 ARCHITECTURE rtl OF test_shifters IS

 COMPONENT pis
 	GENERIC(x : INTEGER);
    	PORT(
		DIN: in std_ulogic_vector (x-1 DOWNTO 0);
		LD,CLK,R,DIR_R,SE: in std_ulogic;
		SO: out std_ulogic
	);
 END COMPONENT;

 COMPONENT sis
 	GENERIC(x : INTEGER);
    	PORT(
		CLK,R,DIR_R,SE,SI: in std_ulogic;
		SO: out std_ulogic
	);
 END COMPONENT;
 
 COMPONENT sisp
 	GENERIC(x : INTEGER);
    	PORt(
		DOUT: OUT STD_ULOGIC_VECTOR ( x-1 DOWNTO 0);
		CLK,R,DIR_R,SE,SI: in std_ulogic;
		SO: out std_ulogic
	);
 END COMPONENT;

 COMPONENT spisp
 	GENERIC(x : INTEGER);
    	PORt(
		DIN: in std_ulogic_vector (x-1 DOWNTO 0);
		DOUT: OUT STD_ULOGIC_VECTOR ( x-1 DOWNTO 0);
		LD,CLK,R,DIR_R,SE,SI: in std_ulogic;
		SO: out std_ulogic
	);
 END COMPONENT;

 FOR siso : sis USE ENTITY WORK.siso(rtl);
 FOR piso : pis USE ENTITY WORK.piso(rtl);
 FOR sispo : sisp USE ENTITY WORK.sispo(rtl);
 FOR spispo : spisp USE ENTITY WORK.spispo(rtl);
 
 SIGNAL CLK : std_ulogic := '0';
 SIGNAL R : std_ulogic;
 SIGNAL DIR_R : std_ulogic;
 SIGNAL LD : std_ulogic;
 SIGNAL SE : std_ulogic;
 SIGNAL SI : std_ulogic;
 SIGNAL SO1 : std_ulogic;
 SIGNAL SO2 : std_ulogic;
 SIGNAL SO3 : std_ulogic;
 SIGNAL SO4 : std_ulogic;
 SIGNAL DIN : std_ulogic_vector( 7  DOWNTO 0);
 SIGNAL DOUT1 : std_ulogic_vector( 7  DOWNTO 0);
 SIGNAL DOUT2 : std_ulogic_vector( 7  DOWNTO 0);
 

 BEGIN

 piso: pis
 	GENERIC MAP (x => 8)
    	PORT MAP (
		DIN => DIN,
		CLK => CLK,
		R => R,
		DIR_R => DIR_R,
		SE => SE,
		LD => LD,
		SO => SO1 
	);


 siso: sis
 	GENERIC MAP  (x => 8)
    	PORT MAP (
		CLK => CLK,
		R => R,
		DIR_R => DIR_R,
		SI => SI,
		SE => SE,
		SO => SO2 
	
	);

 sispo: sisp
 	GENERIC MAP (x => 8)
    	PORT MAP (
		DOUT => DOUT1,
		CLK => CLK,
		R => R,
		DIR_R => DIR_R,
		SI => SI,
		SE => SE,
		SO => SO3 
	);

 spispo: spisp
 	GENERIC MAP (x => 8)
    	PORT MAP (
		DIN => DIN,
		DOUT => DOUT2,
		CLK => CLK,
		R => R,
		DIR_R => DIR_R,
		SI => SI,
		SE => SE,
		LD => LD,
		SO => SO4 
	);





        SI <= 	'1' AFTER 40 ns, 
		'0' AFTER 60 ns,
		'1' AFTER 80 ns,
		'0' AFTER 100 ns,
		'1' AFTER 120 ns,
		'0' AFTER 140 ns,
		'1' AFTER 160 ns;

	DIN <= 	"01010101" AFTER 50 ns;
	LD <= 	'1' AFTER 60 ns,
		'0' AFTER 80 ns;


	SE <=	'1' AFTER 180 ns,
		'0' AFTER 340 ns;
        R <= 	'1' AFTER 20 ns, 
		'0' AFTER 40 ns;
        
	DIR_R <= '1' AFTER 180 ns, 
		 '0' AFTER 220 ns;

	CLK <= NOT CLK AFTER 10 ns;

	
END rtl;