-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : shifters.vhd # -- # # -- # Component : piso : Parallel in - Serial Out shift register with # -- # direction control. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; --************************** -- piso Entity Description * --************************** ENTITY piso IS GENERIC(x : INTEGER := 8); PORt( DIN: IN std_ulogic_vector(x-1 DOWNTO 0); CLK,LD,R,DIR_R,SE: IN STD_ULOGIC; SO: OUT STD_ULOGIC ); END piso; -- piso Architecture Description ARCHITECTURE rtl of PISO IS SIGNAL pre_Q : std_ulogic_vector((x-1) DOWNTO 0) := (OTHERS => 'X'); BEGIN SHIFT_REGISTER_Process: PROCESS(CLK,R) BEGIN IF (R = '1') THEN pre_Q <= (OTHERS => '0'); ELSIF (CLK'event and (CLK = '1') AND (CLK'last_value = '0')) THEN IF (LD = '1') THEN pre_Q <= DIN; ELSIF (SE = '1') AND (DIR_R = '1') THEN pre_Q(x-1) <= '0'; pre_Q((x-2) DOWNTO 0) <= pre_Q((x-1) DOWNTO 1); ELSIF (SE = '1') AND (DIR_R = '0') THEN pre_Q((x-1) DOWNTO 1) <= pre_Q((x-2) DOWNTO 0); pre_Q(0) <= '0'; END IF; END IF; END PROCESS SHIFT_REGISTER_Process; SO <= pre_Q(0) WHEN DIR_R = '1' ELSE pre_Q(x-1) WHEN DIR_R = '0' ELSE 'X'; END rtl;