ENCODERS_DECODERS library
The ENCODERS_DECODERS library consists of the following 3 generic components:
- decN: N input decoder. The input word selects which output bit is asserted.
- decNen: N input decoder. The input word selects which output bit is asserted if allowed by enable. This module can be used as a demultiplexer.
- encN: N input MSB-priority encoder. When no input is asserted the output of the module is 1 (0-), where the number of '0's is log2(N)
The ENC_DECs library can be verified with this testbench: test_encoders_decoders
decN
- encoders_decoders.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : encoders_decoders.vhd # -- # # -- # Component : decN : N-Bit Decoder. The input word selects # -- # which output bit is asserted. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; -- decN Entity Description entity decN is generic(N: INTEGER := 2); port( DIN: in unsigned(log2(N)-1 downto 0); DOUT: out unsigned(N-1 downto 0) ); end decN; -- decN Architecture Description architecture rtl of decN is signal DIN_integer: integer range 0 to N-1; begin DIN_integer <= Conv_Integer('0' & DIN,0); DECODER_process: process (DIN_integer) VARIABLE t : std_ulogic; BEGIN FOR i IN 0 TO N-1 LOOP IF (DIN_integer = i) THEN t := '1'; ELSE t := '0'; END IF; DOUT(i) <= t; END LOOP; end process DECODER_process; end rtl;
decNen
- encoders_decoders.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : encoders_decoders.vhd # -- # # -- # Component : decNen : N-Bit Decoder. The input word selects # -- # which output bit is asserted if allowed # -- # by enable. This module can be used as # -- # demultiplexer. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; -- decNen Entity Description entity decNen is generic(N: INTEGER := 2); port( DIN: in unsigned(log2(N)-1 downto 0); EN: in std_ulogic; DOUT: out unsigned(N-1 downto 0) ); end decNen; -- decNen Architecture Description architecture rtl of decNen is signal DIN_integer: integer range 0 to N-1; begin DIN_integer <= Conv_Integer('0' & DIN,0); DECODER_process: process (DIN_integer, EN) BEGIN FOR i IN 0 TO N-1 LOOP IF EN = '1' AND (DIN_integer = i) THEN DOUT(i) <= '1'; ELSE DOUT(i) <= '0'; END IF; END LOOP; end process DECODER_process; end rtl;
encN
- encoders_decoders.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : encoders_decoders.vhd # -- # # -- # Component : encN : N-bit MSB-priority encoder. When no input # -- # is asserted the module is 1(0...), where # -- # the number of '0's is log2(N). # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; -- encN Entity Description entity encN is generic(N: INTEGER := 4); port( DIN: in unsigned(N-1 downto 0); DOUT: out unsigned(log2(N)-1 downto 0) ); end encN; -- encN Architecture Description architecture rtl of encN is begin PRIORITY_ENCODER_Process: process(DIN) VARIABLE DOUT_int: integer range 0 to N-1; BEGIN DOUT_int := 0; -- for the case that no '1' exists in DIN FOR i IN 0 TO N-1 LOOP IF DIN(i) = '1' THEN -- priority the lowest DIN(i) equal to '1' DOUT_int := i; exit; END IF; END LOOP; DOUT <= Conv_Unsigned(DOUT_int, log2(N)); end process PRIORITY_ENCODER_Process; end rtl;
Testbench
- test_encoders_decoders.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_encoders_decoders.vhd # -- # # -- # Component : test_encoders_decoders : Test Bench for various # -- # encoders/decoders. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; entity test_encoders_decoders IS END test_encoders_decoders; ARCHITECTURE rtl OF test_encoders_decoders IS COMPONENT decN is generic(N: INTEGER := 2); port( DIN: in unsigned(log2(N)-1 downto 0); DOUT: out unsigned(N-1 downto 0) ); end COMPONENT; COMPONENT decNen is generic(N: INTEGER := 2); port( DIN: in unsigned(log2(N)-1 downto 0); EN: in std_ulogic; DOUT: out unsigned(N-1 downto 0) ); end COMPONENT; COMPONENT encN is generic(N: INTEGER := 4); port( DIN: in unsigned(N-1 downto 0); DOUT: out unsigned(log2(N)-1 downto 0) ); END COMPONENT; FOR ALL : decN USE ENTITY WORK.decN(rtl); FOR ALL : decNen USE ENTITY WORK.decNen(rtl); FOR ALL : encN USE ENTITY WORK.encN(rtl); CONSTANT N : integer := 8; SIGNAL DIN1,DOUT3 : unsigned(log2(N)-1 downto 0); SIGNAL DIN3,DOUT1,DOUT2 : unsigned(N-1 downto 0); SIGNAL EN : std_ulogic; BEGIN Decoder : decN GENERIC MAP ( N=>N ) PORT MAP ( DIN=>DIN1, DOUT=>DOUT1 ); Decoder_With_Enable : decNen GENERIC MAP ( N=>N ) PORT MAP ( DIN=>DIN1, EN=>EN, DOUT=>DOUT2 ); Encoder : encN GENERIC MAP ( N=>N ) PORT MAP ( DIN=>DIN3, DOUT=>DOUT3 ); EN <= '1', '0' AFTER 200 ns; DIN1 <= "101", "010" AFTER 100 ns, "110" AFTER 200 ns, "011" AFTER 300 ns; DIN3 <= "00000001", "01000000" AFTER 100 ns, "00010000" AFTER 200 ns, "00000010" AFTER 300 ns; END rtl;