-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    encoders_decoders.vhd                                    #
-- #                                                                          #
-- # Component  :    decN : N-Bit Decoder. The input word selects             #
-- #                        which output bit is asserted.                     #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.all;

-- decN Entity Description
entity decN is
   generic(N: INTEGER := 2);
   port(
      DIN: in unsigned(log2(N)-1 downto 0);
      DOUT: out unsigned(N-1 downto 0)
   );
end decN;

-- decN Architecture Description
architecture rtl of decN is
  signal DIN_integer: integer range 0 to N-1;
begin
  DIN_integer <= Conv_Integer('0' & DIN,0);

  DECODER_process: process (DIN_integer)
  VARIABLE t : std_ulogic;
  BEGIN
    FOR i IN 0 TO N-1 LOOP
      IF (DIN_integer = i) THEN
        t := '1';
      ELSE
        t := '0';
      END IF;
      DOUT(i) <= t;
    END LOOP;
   end process DECODER_process;
end rtl;