-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_encoders_decoders.vhd                               #
-- #                                                                          #
-- # Component  :    test_encoders_decoders : Test Bench for various          #
-- #                                          encoders/decoders.              #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.all;

entity test_encoders_decoders IS
END test_encoders_decoders;

ARCHITECTURE rtl OF test_encoders_decoders IS

COMPONENT decN is
   generic(N: INTEGER := 2);
   port(
      DIN: in unsigned(log2(N)-1 downto 0);
      DOUT: out unsigned(N-1 downto 0)
   );
end COMPONENT;

COMPONENT decNen is
   generic(N: INTEGER := 2);
   port(
      DIN: in unsigned(log2(N)-1 downto 0);
      EN: in std_ulogic;
      DOUT: out unsigned(N-1 downto 0)
   );
end COMPONENT;

COMPONENT encN is
   generic(N: INTEGER := 4);
   port(
      DIN: in unsigned(N-1 downto 0);
      DOUT: out unsigned(log2(N)-1 downto 0)
   );
END COMPONENT;

 FOR ALL : decN USE ENTITY WORK.decN(rtl);
 FOR ALL : decNen USE ENTITY WORK.decNen(rtl);
 FOR ALL : encN USE ENTITY WORK.encN(rtl);
 
 CONSTANT N : integer := 8;
 SIGNAL DIN1,DOUT3 : unsigned(log2(N)-1 downto 0);
 SIGNAL DIN3,DOUT1,DOUT2 : unsigned(N-1 downto 0);
 SIGNAL EN : std_ulogic;
 
 BEGIN

Decoder : decN 
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       DIN=>DIN1,
		       DOUT=>DOUT1
		      );	 

Decoder_With_Enable : decNen
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       DIN=>DIN1,
		       EN=>EN,
		       DOUT=>DOUT2
		      );	 

Encoder : encN
             GENERIC MAP (
                          N=>N
                         )
	     PORT MAP (
		       DIN=>DIN3,
		       DOUT=>DOUT3
		      );	 
		      
EN <= '1', '0' AFTER 200 ns;
    
DIN1 <= "101",
        "010" AFTER 100 ns, 
        "110" AFTER 200 ns, 
        "011" AFTER 300 ns;

DIN3 <= "00000001",
        "01000000" AFTER 100 ns, 
        "00010000" AFTER 200 ns, 
        "00000010" AFTER 300 ns;

END rtl;