MUXERs library
The MUXERs library consists of the following 1 generic component:
- mux_N_W: N-input multiplexer, with W-bits for each input
The MUXERs library can be verified with this testbench: test_muxers
mux_N_W
- muxers.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : muxers.vhd # -- # # -- # Component : muxN_W : N input multiplexer with W bits for each inputs.# -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; -- muxN_W Entity Description entity muxN_W is generic(N: INTEGER := 4; -- Number of input words W: INTEGER := 1);-- Word Width port( INP: in stdv_2d(N-1 downto 0,W-1 downto 0); SEL: in std_ulogic_vector(log2(N)-1 downto 0); DOUT: out std_ulogic_vector(W-1 downto 0) ); end muxN_W; -- muxN_W Architecture Description architecture rtl of muxN_W is begin muxN_W_Process: process(INP,SEL) variable SEL_integer : integer range 0 to N-1; begin SEL_integer := Conv_Integer('0' & SEL,0); for i IN W-1 downto 0 loop -- Assign outputs DOUT(i) <= INP(SEL_integer,i); end loop; end process muxN_W_Process; end rtl;
Testbench
- test_muxers.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_muxers.vhd # -- # # -- # Component : test_muxN_W : Test bench for an N input multiplexer with # -- # W bits for each inputs. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; ENTITY test_muxers IS END test_muxers; ARCHITECTURE rtl OF test_muxers IS COMPONENT mux_4_4 is generic(N: INTEGER := 4; -- Number of input words W: INTEGER := 1);-- Word Width port( INP: in stdv_2d(N-1 downto 0,W-1 downto 0); SEL: in std_ulogic_vector(log2(N)-1 downto 0); DOUT: out std_ulogic_vector(W-1 downto 0) ); END COMPONENT; FOR mux : mux_4_4 USE ENTITY work.muxN_W(rtl); CONSTANT N : integer := 4; CONSTANT W : integer := 4; SIGNAL INP: stdv_2d(N-1 downto 0,W-1 downto 0); SIGNAL SEL: std_ulogic_vector(log2(N)-1 downto 0); SIGNAL DOUT: std_ulogic_vector(W-1 downto 0); BEGIN mux : mux_4_4 GENERIC MAP(N => N, W => W) port map( INP => INP, SEL => SEL, DOUT => DOUT); SEL <="11" AFTER 0150 ns, "10" AFTER 0200 ns, "01" AFTER 0250 ns, "00" AFTER 0300 ns, "ZZ" AFTER 0350 ns; INP <= ("0000","1111","0011","1100"); END rtl;