-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    muxers.vhd                                               #
-- #                                                                          #
-- # Component  :    muxN_W : N input multiplexer with W bits for each inputs.#
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.all;

-- muxN_W Entity Description
entity muxN_W is
   generic(N: INTEGER := 4; -- Number of input words
           W: INTEGER := 1);-- Word Width
   port(
      INP: in stdv_2d(N-1 downto 0,W-1 downto 0);
      SEL: in std_ulogic_vector(log2(N)-1 downto 0);
      DOUT: out std_ulogic_vector(W-1 downto 0)
   );
end muxN_W;

-- muxN_W Architecture Description
architecture rtl of muxN_W is
 
begin
   muxN_W_Process: process(INP,SEL)
      variable SEL_integer : integer range 0 to N-1;
   begin
      SEL_integer := Conv_Integer('0' & SEL,0);
      for i IN W-1 downto 0 loop
        -- Assign outputs
        DOUT(i) <= INP(SEL_integer,i);
      end loop;       
   end process muxN_W_Process;
end rtl;