courses:system_design:vhdl_language_and_syntax:sequential_statements:variables

Variables

Fundamentals

architecture RTL of XYZ is
  signal A, B, C : integer range 0 to 7;
  signal Y, Z    : integer range 0 to 15;
begin
  process (A, B, C)
    variable M, N : integer range 0 to 7;
  begin
    M := A;
    N := B;
    Z <= M + N;
    M := C;
    Y <= M + N;
  end process;
end RTL;

Variables

  • Variables are only available within processes:
    • Name within process declarations
    • Known only in this process
VHDL’93: shared variables
  • Immediate assignment
  • Keep the last value
  • Possible assignments:
    • Signal to variable
    • Variable to signal
    • Types have to match

Notes

Variables can only be defined in a process and they are only accessible within this process.

Variables and signals show a fundamentally different behavior. In a process, the last signal assignment to a signal is carried out when the process execution is suspended. Value assignments to variables, however, are carried out immediately. To distinguish between a signal and a variable assignment different symbols are used: ’⇐’ indicates a signal assignment and ’:=’ indicates a variable assignment.

Variables vs. Signals

signal A,B,C: integer; 
signal Y, Z : integer; 
 
begin                     
  process (A,B,C)
    variable M, N:
             integer;     
  begin                     
    M := A;                 
    N := B;                 
    Z <= M + N;             
    M := C;                 
    Y <= M + N;           
  end process;
 
signal A,B,C: integer; 
signal Y, Z : integer; 
signal M, N : integer;
begin                     
  process (A,B,C,M,N)
 
 
  begin                     
    M <= A;                 
    N <= B;                 
    Z <= M + N;             
    M <= C;                 
    Y <= M + N;           
  end process;
Variables Signals
  • Signal values are assigned after the process execution
  • Only the last signal assignment is carried out
  • M ⇐ A; is overwritten by M ⇐ C;
  • The 2nd adder input is connected to C

Notes

The two processes shown in the example implement different behavior as both outputs Z and Y will be set to the result of B+C when signals are used instead of variables.

Please note that the intermediate signals have to added to the sensitivity list, as they are read during process execution.

Use of Variables

Use of Variables

  • intermediate results of algorithm implementations
    • signal to variable assignment
    • execution of algorithm
    • variable to signal assignments
  • no access to variable values outside their process
  • variables store their value until the next process call

Notes

Variables are especially suited for the implementation of algorithms. Usually, the signal values are copied into variables before the algorithm is carried out.

The result is assigned to a signal again afterwards.

Variables keep their value from one process call to the next, i.e. if a variable is read before a value has been assigned, the variable will have to show storage behavior. That means it will have to be synthesized to a latch or flip flop respectively.

Variables: Example

  • Parity calculation
entity PARITY is
  port (DATA: in bit_vector (3 downto 0);
       ODD : out bit);
end PARITY;
 
architecture RTL of PARITY is
begin
  process (DATA)
    variable TMP : bit;
  begin
    TMP := ‘0’;
    for I in DATA’low to DATA’high loop
      TMP := TMP xor DATA(I);
    end loop;
    ODD <= TMP;
  end process;
end RTL;
  • Synthesis result:

Synthesis result

Notes

In the example a further difference between signals and variables is shown. While a (scalar) signal can always be associated with a line, this is not valid for variables. In the example the for loop is executed four times. Each time the variable TMP describes a different line of the resulting hardware. The different lines are the outputs of the corresponding XOR gates.

Shared Variables (VHDL’93)

architecture BEHAVE of SHARED is
  shared variable S : integer;
begin
  process (A, B)
  begin
    S := A + B;
  end process;
 
  process (A, B)
  begin
    S := A - B;
  end process;
end BEHAVE;
  • Accessible by all processes of an architecture (shared variables)
  • Can introduce non determinism
Not to be used in synthesizable code

Notes

In VHDL 93, global variables are allowed.

These variables are not only visible within a process but within the entire architecture.

The problem may occur, that two processes assign a different value to a global variable at the same time. It is not clear then, which of these processes assigns the value to the variable last.

This can lead to a non deterministic behavior!

In synthesizable VHDL code global variables must not be used.

Chapters of System Design > VHDL Language and Syntax > Sequential Statements

Chapters of System Design > VHDL Language and Syntax