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courses:system_design:vhdl_language_and_syntax:sequential_statements:quiz

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Quiz

Sequential statements ...

...can be anywhere in the statement part of an architecture.
...are always described with variables, because they need instant (sequential) value update.
neither of them

Loops ...

...with infinite passed are not synthesizable
...do not need to declare the loop identifier in the architecture declarative part

A process ...

...can either have a sensitivity list or wait statements but not both.
...with wait statements is executed until the timing conditions in the wait statements are fulfilled and retired afterwards.

Variables ...

...are only accessible within the process that declared them.
...can not be assigned to signals because of the signal update problem.
... are reinitialized whenever the process is executed.

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Chapters of System Design > VHDL Language and Syntax > Sequential Statements

Sequential Statements
IF Statement
CASE Statement
FOR Loops
WAIT Statement
Variables
Quiz

Chapters of System Design > VHDL Language and Syntax

General Issues
VHDL Structural Elements
Data Types
Process Execution
Extended Data Types
Operators
Sequential Statements
Subprograms
Subprogram Declaration and Overloading
Concurrent Statements

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