courses:system_design:synthesis:master-slave_flip-flop:toggle-ff

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T=J=K

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T C Q(t+1) state
1 Q'(t) invert
0 Q(t) hold

↑ = rising edge of clock

  • Q(t+1)=[(Q' and T) or (Q and T')](t) = Q(t) xor T(t)

Asynchronous 4 bit binary counter block diagram

Asynchronous 4 bit binary counter timing behaviour

simple structure - but problems by application because of real runtimes!!!!

JK-FF with Reset:

U_D_MS: D_MS
     port map (CLK, D, Q, Qn);
 
  D <= '0' when RESET = '1' 
           else (Qn and J) or (Q and not K);

Synchronous 4 bit binary counter with Reset

Timing Behaviour


Chapters of System Design > Synthesis > Master-Slave Flip-Flop