× Quiz A registered output of a state machine ... ... creates unnecessary flipflops ... prevents transmission of spikes created during evaluation of the state. ... is always slower than a state machine without registered output If generate statements ... ... never have an else path ... must cover all possibilities of the condition Check answers You Scored % - / Chapters of System Design > Synthesis RTL-Style What is Synthesis Finite State Machines and VHDL Combinational Logic Sequential Logic Advanced Synthesis Controlling Synthesis Master-Slave Flip-Flop Quiz