courses:system_design:simulation:simulation_flow

Signal Flow

Fundamentals

Signal Flow

The simulation of a VHDL model operates in three phases.

  1. Design elaboration
    • Specified elements are created
  2. Signal initialisation
    • Starting values are assigned
  3. Simulation is executed on command

Elaboration

Elaboration

  • During elaboration design elements are created
  • All design objects are elaborated before the simulation
  • Except “for loop”- variables and objects which are defined in subprograms

Notes

First, the simulation model is created in the elaboration phase. The processes and concurrent statements of the whole design are combined in a communication model. This model lists, which process can be activated by which one, i.e. some sort of netlist is created. All objects are converted to an executable form residing in the simulator memory. Loop variables and subprograms are the only exception as they are elaborated dynamically during the execution of the simulation.

Initialization

Initialization 

type std_ulogic is (’u’,’x’,’0’.....)
               -- First value is ’u’ !!!
signal clock: std_ulogic := ’0’;
signal reset: std_ulogic;
  • Initial values:
    • Start values from declaration OR
    • First value from type definition (type’left)
  • Every process is executed until it is suspended
    • … without signal values being updated

Notes

The initial values of all signals are assigned in the initialization phase.

Either the initial value specified in the signal declaration or the first value in the type definition (=“data type’left”) is used. In the case of the type STD_ULOGIC based types this is an ’u’ for uninitialized.

Hence the designer can deduce from an ’u’ in the simulation waveform, that there has never been assigned a value to the corresponding signal. Signal values do not return to ’u’ except an ’u’ is directly assigned.

Execution

Execution

  • Simulation is actually executed
  • Signal values are evaluated

Notes

At the end of the initialization phase every process is executed once until it is suspended.

The signal values, however, are not updated. The actual simulation of the design behavior takes place in the execution phase.

By means of testbench processes, the VHDL model is provided with stimuli.

The individual signals of the model can then be viewed and checked in the waveform window (stimuli and responses of the model).

The actual responses can be compared automatically with the expected values by adequate VHDL statements, as well.

For instance you can compare actual and expected responses at time OCCURRING_TIME by an assertion in an 'if' statement: 

if now=OCCURRING_TIME then
   assert EXPECTED_RESPONSE=RECEIVED_RESPONSE
   report "unexpected behaviour"
   severity error;
end if;

Chapters of System Design > Simulation